Swamy Baldev, Shukla Kaustub, Sushanta Gogai, Pradeep Rathore, Rangababu Peesapati, Design and Implementation of Efficient Streaming Deblocking and SAO Filter for HEVC Decoder, IEEE Transactions on Consumer Electronics, 64, 1, Page Nos -1-9, 2018.
Sasidhar M, Pradeep Rathore, Rangababu Peesapati, Decimal Multiplication using Compressor based-BCD to Binary Converte, International Journal of Engineering Science and Technology (Elsevier)), Early Access, Page Nos -1-6, 2018. https://www.sciencedirect.com/science/article/pii/S2215098617312181
S. Gautam, A.Gupta, S. Majumdar, A. Patraa, R. Dhabalia, J. Teraiya, Prediction of particulate matter concentration profile in an opencast copper mine in India using an artificial neural network model, Recycle - International conference on waste management, 22Feb - 24Feb, IIT Guwahati, Page Nos --, 2018.
A. Sarkhel; S. R. B. Chaudhuri, Compact Quad-Band Polarization-Insensitive Ultrathin Metamaterial Absorber With Wide Angle Stability, IEEE Antenna & Wireless Propagation Letters, 16, Page Nos -3240 - 3244, 2017.
M. Mishra, S. Majumdar, D. Malviya, P.P. Bansod, Design of SRAM Cell in 0.18 μm Technology, International Conference on Information, Communication and Embedded System, 23 Feb - 24 Feb, Chennai, Page Nos -457-463, 2012.
D.Malviya, S. Majumdar, M. Mishra, P.P. Bansod, Comparative Study on Implementation of Various Decoder Architecture, International Conference on Information, Communication and Embedded System, 23 Feb - 24 Feb, Chennai, Page Nos -68-74, 2012.
S. Majumdar, D. Malviya, M. Mishra, P.P. Bansod, Designing of Control Logic Circuit for SRAM Memory Cell, International Conference on Information, Communication and Embedded System, 23 Feb - 24 Feb, Chennai, Page Nos -375-381, 2012.
S. Majumdar, S. Sheikh, S. Ghosh, D. Biswas, Determination of Polarity and Defect Density via Molten KOH Etching of MBE Grown AlN Layer, International Workshop on the Physics of Semiconductor Devices (IWPSD), Dec 7- Dec10, IISc Bangalore, Page Nos -66, 2015.
S. Majumdar, P. Das, D. Biswas, Cap layer Engineering : Performance Evaluation of E-Mode InGaN/AlGaN/GaN HEMT, 1st National Conference on Device and Circuits, Feb 19, NIST Behrampur, Page Nos -1-4, 2015.
A. Chakradhari, S. Tamrakar, R. Basant, M. Vaidya, S. Majumdar, A. Naugarhiya, B. Acharya, S. Majumder, S. Verma, Slotted CSMA/CA Simulation in Verilog, International Workshop on Internet of Things and TV White Spaces (WIOT’ 2017)., Jan 12- Jan 13, Pune, Page Nos -1, 2017.
A. Sharma, S. Majumdar, A. Naugarhiya, B. Acharya, S. Majumder, S. Verma, VERILOG based simulation of ASK, FSK, PSK, QPSK digital modulation techniques, International conference on IoT in Social, Mobile, Analytics and Cloud (I-SMAC 2017), 10 Feb- 11 Feb, Coimbatore, Page Nos -403-408, 2017. https://doi.org/10.1109/I-SMAC.2017.8058380
A. Chaudhary, J. Rusia, K. Gourav, P. Tripathi, J. Pandey, S. Majumdar, A. Naugarhiya, B. Acharya, S. Majumder, S. Verma, Design and Simulation of Physical Layer Blocks of ZigBee Transmitter, International conference on IoT in Social, Mobile, Analytics and Cloud (I-SMAC 2017), 10 Feb- 11 Feb, Coimbatore, Page Nos -347-351, 2017. https://doi.org/10.1109/I-SMAC.2017.8058369
J. Rusia, S. Majumdar, A. Naugarhiya, B. Acharya, S. Majumder, S. Verma, RF Based Wireless Data Transmission between Two FPGAs, International Conference on ICT in Business Industry Government (ICTBIG 2016), 18 Dec - 19 Dec, Indore, Page Nos -1-5, 2016. http://ieeexplore.ieee.org/document/7892643/
J. Rusia, S. Majumdar, A. Naugarhiya, B. Acharya, S. Majumder, S. Verma, Remote Temperature & Humidity sensing through ASK Modulation Technique, International Conference on ICT in Business Industry Government (ICTBIG 2016), 18 Dec - 19 Dec, Indore, Page Nos -1-5, 2016. http://ieeexplore.ieee.org/document/7892642/
S.Das, S.Majumdar, R. Kumar, M. K. Mahata, S. M. Dinara, D. Biswas, Comprehensive modeling of gas sensor based on Si3N4 passivated AlGaN/GaN Schottky diode, IEEE 2nd International Conference on Emerging Electronics, 3 Dec - 6 Dec, IISc Bangalore, Page Nos -1-4, 2014. https://doi.org/10.1109/ICEmElec.2014.7151192
S. Majumdar, P. Bansod, Hardwired BIST Architecture of SRAM, 11th Indicon, 11-13 Dec, IEEE Pune Section, Page Nos -1-6, 2014. https://doi.org/10.1109/INDICON.2014.7030466
S. Das, S. Majumdar, R. Kumar, A. Chakraborty, A. Bag, D. Biswas, Simpli?ed gas sensor model based on AlGaN/GaN heterostructure Schottky diode, 4th National Conference on Advanced Materials and Radiation Physics, 13 - 14 March, SLIET Longowal, Page Nos -020014, 2015. http://aip.scitation.org/doi/10.1063/1.4929172
S. Majumdar, S. Shaik, S. Das, R. Kumar, A. Bag, A. Chakraborty, M. Mahata S. Ghosh, D. Biswas, Temperature dependent etching of Gallium Nitride layers grown by PA – MBE, International Conference on Microwave and Photonics (ICMAP-2015), 11-13 Dec, ISM Dhanbad, Page Nos -1-3, 2015. https://doi.org/10.1109/ICMAP.2015.7408773
S.Majumdar, M.Zuhair, D.Biswas, Arti?cial neural network modelling of ADS designed Double Pole Double Throw switch, 18th International Symposium on VLSI Design and Test (VDAT), 16 Jul - 18 Jul, Coimbatore, Page Nos -1-2, 2014. https://doi.org/10.1109/ISVDAT.2014.6881066
A. Bag, P. Mukhopadhyay, S. Majumdar, D. Biswas, Role of Bulk Traps on Intermodulation Distortion of AlGaN/GaN HEMT, Material Research Society Fall Meeting, 29 Nov.- 4 Dec., Boston, Massachusetts, Page Nos -RR. 03, 2015. http://www.mrs.org/fall-2015
S.Ghosh, S.Das, P.Mukhopadhyay, A.Bag, S.Majumdar, D.Biswas, Electrical Degradation Mechanism of GaN High Electron Mobility Transistors on Silicon and Sapphire under OFF-state Stress, Material Research Society Fall Meeting, 29 Nov.- 4 Dec., Boston, Massachusetts, Page Nos -RR. 1.09, 2015. http://www.mrs.org/fall-2015
S.Das, R.Kumar, S. Majumdar, M.Mahata, S.Ghosh, D.Biswas, Acetone sensing in AlGaN/GaN heterostructure on Si (111) : A Schottky diode sensor, European Material Research Society Fall Meeting, 15 Sep.-18 Sep, Warsaw, Poland, Page Nos -O.O.7, 2015. https://www.european-mrs.com/2015-fall-symposium-n-european-materials-research-society
S. Majumdar, S. Das, D. Biswas, Barrier layer engineering : Performance evaluation of E-mode InGaN/AlGaN/GaN HEMT, 4th National Conference on Advanced Materials and Radiation Physics, 13 - 14 March, SLIET Longowal, Page Nos -020021, 2015. http://aip.scitation.org/doi/10.1063/1.4929179
S. Majumdar, R. Kumar, S.Das, M. Mahata, D. Biswas, Utilization of Support Vector Machine in determining the optimum operating temperature of ternary III-Arsenide alloys grown by MBE, European Material Research Society Fall Meeting, 15 Sep.-18 Sep, Warsaw, Poland, Page Nos -N.N.8, 2015. https://www.european-mrs.com/2015-fall-symposium-n-european-materials-research-society
S.Majumdar, C. Sahu, D.Biswas, Fabrication of E-mode InGaN/AlGaN/GaN HEMT using FIB based Lithography, Electron Devices Technology and Manufacturing Conference EDTM 2017, 28 Feb.-2 March, Toyama, Japan, Page Nos -175-177, 2017. 10.1109/EDTM.2017.7947579
S. Majumdar, M. Khalid, A Novel Sequence Generator Replacing LFSR For Hardwired BIST Of SRAM, International Journal of Engineering Research and Applications, 2, 6, Page Nos -822-826, 2012.
S. Majumdar, D. Biswas, Performance Variability Projection of InGaN/AlGaN/GaN E-mode HEMT for RF Switch Application, ECS Solid State Letters, 4, 10, Page Nos -P72-P74, 2015. http://ssl.ecsdl.org/content/4/10/P72.short
S. Majumdar, A. Bag, D. Biswas, Implementation Of VerilogA GaN HEMT Model To Design RF Switch, Microwave and Optical Technology Letters, 57, 7, Page Nos -1765-1768, 2015. http://onlinelibrary.wiley.com/doi/10.1002/mop.29152/full
A. Bag, P. Das, R. Kumar, P. Mukhopadhyay, S. Majumdar, S. Kabi, D. Biswas, 2DEG modulation in double quantum well enhancement mode nitride HEMT, Physica E Low-dimensional Systems and Nanostructures, 74, Page Nos -59-64, 2015. https://doi.org/10.1016/j.physe.2015.06.011
A. Patra, S. Gautam, S. Majumdar, P. Kumar, Prediction of particulate matter concentration pro?le in an opencast copper mine in India using an arti?cial neural network model, Air Quality, Atmosphere & Health, 9, Page Nos -697–711, 2016. https://link.springer.com/article/10.1007%2Fs11869-015-0369-9
S.Das, S. Majumdar, R.Kumar, S.Ghosh, D.Biswas, Thermodynamic Analysis of Acetone sensing in Pd/AlGaN/GaN heterostructure Schottky diodes at low temperatures, Scripta Materialia, 113, Page Nos -39-42, 2016. https://doi.org/10.1016/j.scriptamat.2015.10.015
S. M. Dinara, S.Ghosh, S. K. Jana, S. Majumdar, D. Biswas, S. Bhattacharya, Analysis of strain induced carrier con?nement with varying passivation thickness of the Al0.3Ga0.7N /GaN heterostructure with graded AlxGa1-xN bu?er on Si (111) substrate, Journal of Vaccum Science & Technology (JVST) B- AVS: Science & Technology of Materials, Interfaces, and Processing, 35, 5, Page Nos -051202, 2017. http://avs.scitation.org/doi/full/10.1116/1.4996735
A. Bag, S. Majumdar, S. Das, D. Biswas, Probing InGaN immiscibility at AlGaN/InGaN heterointerface on silicon (111) through two-step capacitance-voltage and conductance-voltage profiles, Materials & Design, 133, Page Nos -176-185, 2017. https://doi.org/10.1016/j.matdes.2017.07.061
S. Majumdar, D. Biswas, Evaluating Substrate‘s E?ect on RF Switch Performance via Verilog-A GaN HEMT Model, Microelectronics Journal, 62, Page Nos -43-48, 2017. https://doi.org/10.1016/j.mejo.2017.02.007
S. Majumdar, A. Bag, D. Biswas, Comparative Analysis of Parameter Extraction Techniques for AlGaN/GaN HEMT on silicon/sapphire substrate, Microelectronics Reliability, 78, Page Nos -389-395, 2017. https://doi.org/10.1016/j.microrel.2017.08.016
Satabdy Jena, Gayadhar Panda, Rangababu Peesapati, FPGA based implementation for Improved control scheme of grid-connected PV system with three-phase three-level NPC-VSI, International Journal of Circuit Theory Applications (IJCTA), Willey Blackwell), Early Access, Page Nos -1-26, 2018. http://onlinelibrary.wiley.com/doi/10.1002/cta.2448/full
D. Kumar, P. Saha and A. Dandapat, Vedic Algorithm for Cubic Computation and VLSI Implementation, Engineering Science and Technology, an International Journal, Elsevier, XX, XX, Page Nos -XX, 2017.
S. Mishra, T. V. Mahendra, J. Saikia, and A. Dandapat, A Low-Overhead Dynamic TCAM with Pipelined Read-Restore Refresh Scheme, IEEE Transactions on Circuits and Systems I: Regular Papers, PP, 99, Page Nos -1-22, 2017. https://doi.org/10.1109/TCSI.2017.2756662
Rangababu Peesapati, Sonketa Das, Swamy Baldev, Shaik Rafi Ahamed, Design of Streaming Deblocking Filter for HEVC Decoder, IEEE Transactions on Consumer Electronics, 63, 3, Page Nos -1-9, 2017. http://ieeexplore.ieee.org/abstract/document/8103370/
V. Kumar, K. L. Baishnab and B. Kumar, A Novel Shared Active Pixel Architecture (SAPA) with Low Dark Current and High Fill-Factor (FF) for CMOS Image Sensors, Journal of Low Power Electronics, 13, 3, Page Nos -490-496, 2017. http://www.ingentaconnect.com/content/asp/jolpe/2017/00000013/00000003/art00018
V. Anil Kumar, Ch. V. Rama Rao, Unsupervised noise removal technique based on constrained NMF, IET Signal Processing, ,, 2017. digital-library.theiet.org/content/journals/10.1049/iet-spr.2016.0414
V. Anil Kumar, Ch. V. Rama Rao, and Anirban Dutta, Performance analysis of blind source separation using canonical correlation, Springer, Circuits, Systems, and Signal Processing, ,, 34, Page Nos -1-16, 2017. https://link.springer.com/article/10.1007/s00034-017-0566-x
Kiran kumar Anumandla, Rangababu Peesapati, Samrat L Saba, Hardware Implementation of Multi-Objective Differential Evolution algorithm: A Case Study of Spectrum Allocation in Cognitive Radio Networks, International Journal of Innovative Computing and Applications (Inderscience), 8, 4, Page Nos -241-253, 2017. https://www.inderscienceonline.com/doi/abs/10.1504/IJICA.2017.088176
V. Kumar, Md. A. Laskar, Y. Singh,S. Majumdar and S. K. Sarkar, ANN Based Adaptive Detection of ECG Features from Respiratory, Pleythsmographic and ABP Signals [Chapter], Springer, 978-3-319-11932-8 (Print), 978-3-319-11933-5 (Online), 359 - 365, Page Nos -2015
Rituparna choudary, Rangababu P, Design and Implementation of Mixed Parallel and Dataflow Architecture for Intra-prediction Hardware in HEVC Decoder, International Symposium on VLSI Design and Test, 29-06-2017 to 2-07-2017, IIT Roorkee, Page Nos -557-569, 2017. https://link.springer.com/chapter/10.1007/978-981-10-7470-7_70
Puja ghosh, Rangababu P, Design and Implementation of Ternary Content Addressable Memory (TCAM) based Hierarchical Motion Estimation for Video Processing, International Symposium on VLSI Design and Test, 29-06-2017 to 2-07-2017, IIT Roorkee, Page Nos -742-750, 2017. https://link.springer.com/chapter/10.1007/978-981-10-7470-7_54
T. V. Mahendra, S. Mishra, and A. Dandapat, Self controlled high performance pre-charge free content addressable memory, IEEE Transactions on Very Large Scale Integration (VLSI) Systems, PP, 99, Page Nos -1-5, 2017. https://doi.org/10.1109/TVLSI.2017.2685427
V. Anil Kumar, Ch. V. Rama Rao, Blind speech separation using canonical correlation and performance analysis, IEEE International Conference CSCITA-2017, April 7-8, Mumbai, 2017.
Kambam Bijen Singh, Telajala Venkata Mahendra, Ravi Singh Kurmvanshi and Ch V Rama Rao, Image Enhancement with the Application of Local and Global Enhancement Methods for Dark Images, IEEE International Conference on Innovations in Electronics, Signal Processing and Communication (IESC 2017), April 6-7, Shillong, 2017.
kambam Bijen Singh, Sheikh Wasmir, Telajala Venkata Mahendra and Ch V Rama Rao, Implementation of OFDM and Pulsed-OFDM, IEEE 15th International Conference on Information Technology (ICIT), Dec. 22-24, Bhubaneswar, 2016.
Smitha Joyce Pinto, Gayadhar Panda, Rangababu Peesapati, An Implementation of Hybrid Control Strategy for Distributed Generation System Interface Using Xilinx System Generator, IEEE Transactions on Industrial Informatics, 13, 5, Page Nos -2735-2745, 2017. ieeexplore.ieee.org/abstract/document/7968306/
Shuchishman Burman, Rangababu Peesapati and Kamalika Datta, Development of Dynamic Reconfiguration Implementation of AES on FPGA Platform, In Proceedings of International Conference on Devices for Integrated Circuit (DevIC, 23rd-24th March, Kolkata, Page Nos -247-251, 2017.
Rubina Khongsit, P.Rangababu, Scalable Discrete Tchebichef Transform for Image/Video Compression, In Proceedings of International Conference on Innovations in Electronics, Signal Processing and Communication(IESC), 6th-7th April, Shillong, Page Nos -127-131, 2017.
K Shukla, Swamy Baldev, Rangababu P, Area Efficient Dataflow Hardware Design of SAO Filter for HEVC, In Proceedings of International Conference on Innovations in Electronics, Signal Processing and Communication, 6th-7th April, Shillong, Page Nos -16-21, 2017.
J. Saikia, S. Mishra, and A. Dandapat, Large Scale Dynamic Content Addressable Memory with Hybrid Matchline Structure, Students' Technology Symposium (TechSym), 2016 IEEE, Oct, Kharagpur, India, 2016.
V. M. Tripathi, S. Mishra, J. Saikia, and A. Dandapat, A Low-Voltage 13T Latch-Type Sense Amplifier with Regenerative Feedback for Ultra Speed Memory Access, 2017 30th International Conference on VLSI Design and 2017 16th International Conference on Embedded Systems (VLSID), Jan, Hyderabad, India, Page Nos -341-346, 2017.
A. Gogoi and V. Kumar, Design of Low Power, Area Efficient and High Speed Approximate Adders for Inexact Computing, IEEE International Conference on Signal Processing and Communication (ICSC 2016), 26th-28th December, Noida, Uttar Pradesh, 2016. http://ieeexplore.ieee.org/document/7980623/
Satabdy Jena, Gayadhar Panda, Rangababu Peesapati, Investigation on FPGA based Passive AntiIslandingProtection Schemes for Grid Interfaced Distributed Generation System, In Proceedings of IEEE International Conference on TENCON, Nov 22-25, Singapore, Page Nos -1439-1444, 2016.
Rangababu Peesapati, Kiran kumar Anumandla, Samrat L. Sabat, Performance Evaluation of Floating Point Differential Evolution Hardware Accelerator on FPGA, In Proceedings of IEEE International Conference on TENCON, Nov 22-25, Singapore, Page Nos -3173-3178, 2016.
A. Sarkhel, S. R. B. Chaudhuri, Magnetic Response of Rectangular and Circular Split Ring Resonator: A Research Study, International Conference on Communication, Circuits and Systems, October 5-7, Bhubaneswar,India, 2012.
A. Sarkhel and S. R. B. Chaudhuri, Enhanced Gain Printed Slot Antenna Using an Electric Metasurface Superstrate, Springer: Applied Physics A, 122, 10, Page Nos -122: 934, 2016.
V. Kumar, C. K. Jha, G. Thapa, A. Dandapat, Design of Low Power and High Speed Carry Look Ahead Adder (CLA) Using Hybrid CMOS Logic Style [Chapter], Springer, 978-81-322-2726-7 (Print), 978-81-322-2728-1 (Online), 645-654, Page Nos -2016
V. Kumar, C. K. Jha, G. Thapa, A. Dandapat, A Novel Methodology for Design of Cyclic Combinational Circuits, Journal of Low Power Electronics, 12, 3, Page Nos -205-217 (13), 2016. http://www.ingentaconnect.com/contentone/asp/jolpe/2016/00000012/00000003/art00005
V. Kumar, A. Dandapat, Design Methodology for Multiple Output Combinational Circuits Using Cyclic Combinational Technique, Journal of Circuits, Systems, and Computers, 25, 12, Page Nos -1-20, 2016. http://www.worldscientific.com/doi/abs/10.1142/S021812661650153X
V. Kumar, C. K. Jha, G. Thapa, A. Dandapat, Design of Low Power and High Speed Carry Look Ahead Adder (CLAA) Based on Hybrid CMOS Logic Style, Springer India, 978-81-322-2728-1, 645-654, Page Nos -2016
S. Mishra and A. Dandapat, Energy-efficient adaptive match-line controller for large-scale associative storage, IEEE Transactions on Circuits and Systems II: Express Briefs, 64, 6, Page Nos -710-714, 2017. http://dx.doi.org/10.1109/TCSII.2016.2595598
T. V. Mahendra, S. Mishra, and A. Dandapat, Fully Dynamic High Density Associative Storage Architectures: Study, Comparison and a Proposal, Electronics and Communication Systems (ICECS), 2016 3rd International Conference on, Feb, Coimbatore, India, Page Nos -3401-3404, 2016.
M. Chanda, S. Jain and A. Dandapat, Implementation of modified Low power 8 X 8 signed DADDA multiplier, International Journal on Electronic and Electrical Engineering, 7, ?, Page Nos -7, 2010.
D. Kayal, S. Chowdhury, A. Dandapat, C. K. Sarkar, A High Speed High Performence 8bit Multiplier Using MCcmos Technique, International Journal of Computer Engineering and Computer Applications, 4, 1, Page Nos -5, 2010.
P. Saha, A. Banerjee, A. Dandapat and P. Bhattacharrya, Vedic Mathematics Based 32-Bit Multiplier Design for High Speed Low Power Processors, International Journal of smart sensing and intelligent systems, 4, 2, Page Nos -16, 2011.
S. Rabbani, P.K. Rathore, G. Ghosh, B.S. Panwar, MEMS structure for energy harvesting, COMSOL Conference 2010, 29-30 October 2010, Bangalore, India, Page Nos -1-5, 2010.
B.S. Panwar, P.K. Rathore, P. Varshney, S. Prasad, Modeling and Simulation of a Wideband PZT Micro-Cantilever Structure for Energy Harvesting, Indo-French Symposium on Sensors Technologies and Systems (IFS12), March 1-4, 2012, Indian Institute of Technology Delhi, Page Nos -48-49, 2012.
P. Varshney, B.S. Panwar, P. Rathore, S. Ballandras, B. Francois, G. Martin, J.M. Friedt, T. Retornaz, Theoretical and experimental analysis of high Q SAW resonator transient response in a wireless sensor interrogation application, IEEE Frequency Control Symposium (IFCS-2012), May 21-24, 2012, Baltimore, Maryland, USA, Page Nos -1-6, 2012.
P.K. Rathore, B.S. Panwar, CMOS-MEMS based Current Mirror MOSFET Embedded Pressure Sensor for Healthcare and Biomedical Applications, International Conference on Biomaterial and Bioengineering (ICBB-2012), December 19-20, 2012, Hong Kong, China, Page Nos -315-320, 2012.
P.K. Rathore, B.S. Panwar, Design and optimization of CMOS-MEMS integrated current mirror sensing based MOSFET embedded pressure sensor, IEEE Multi-Conferences on Sensing and Control (MSC-2013), August 28-30, 2013, Hyderabad, India, Page Nos -443-448, 2013.
P.K. Rathore, B.S. Panwar, H.J. Pandya, High Sensitivity Square Ring Channel Shaped MOSFET Embedded Pressure Sensor Integrated with a Current Mirror Readout Circuitry, IEEE Sensors 2013 (SENSORS-2013), November 3-6, 2013, Baltimore, Maryland, USA, Page Nos -1066-1069, 2013.
P.K. Rathore, B.S. Panwar, CMOS-MEMS Integrated MOSFET Embedded Bridge Structure based Pressure Sensor, IEEE Annual IEEE India Conference 2013 (INDICON-2013), December 13-15, 2013, Indian Institute of Technology Bombay, Page Nos -1-6, 2013.
P.K. Rathore, B.S. Panwar, High Sensitivity CMOS Pressure Sensor Using Ring Channel Shaped MOSFET Embedded Sensing, 2014 IEEE International Conference on Electronics, Computing and Communication Technologies (CONECCT 2014), January 6-7, 2014, Indian Institute of Science Bangalore, Page Nos -1-5, 2016.
S. Kumar, P.K. Rathore, J. Akhtar, A comparative study on p- and n-channel MOSFET embedded pressure sensing structures integrated with current mirror readout circuitry, 2016 IEEE International Students’ Conference on Electrical, Electronics and Computer Science (SCEECS-2016), March 5-6, 2016, Maulana Azad National Institute of Technology Bhopal, 2016.
P.K. Rathore, J. Akhtar, Fabrication of a membrane type double cavity vacuum sealed micro sensor for absolute pressure based on front-side lateral etching technology, Sensor Review, 31, 1, Page Nos -41-46, 2011.
P.K. Rathore, P. Varshney, S. Prasad, B.S. Panwar, Finite element method based absolute pressure sensitivity optimized membrane type double cavity vacuum sealed piezoresistive sensor, Sensor Review, 33, 4, Page Nos -352-362, 2013.
P.K. Rathore, B.S. Panwar, CMOS-MEMS based current mirror MOSFET embedded pressure sensor for healthcare and biomedical applications, Advance Materials Research, 647, Page Nos -315-320, 2013.
P.K. Rathore, B.S. Panwar, J. Akhtar, A Novel CMOS-MEMS Integrated Pressure Sensing Structure Based On Current Mirror Sensing Technique, Microelectronics International Journal, 32, 2, Page Nos -81-95, 2015.
A. Sarkhel, S. R. B. Chaudhuri, Design of Miniaturized PIFA with Magnetic Resonator Metamaterial Loading, IEEE Applied Electromagnetics Conference, December 18-21, Guwahati,India, 2015.
B. Pushpa Devi, Kh. Manglem Singh and Sutipta Roy, A Watermarking Scheme for Digital Images based on Visual Cryptography based on Singular Value decomposition, Contemporary Engineering Sciences, 8, 32, Page Nos -1517 – 1528, 2015.
B. Pushpa Devi, Kh. Manglem Singh and Sutipta Roy, Dual Image Watermarking scheme based on Singular Value decomposition and Visual cryptography in Discrete Wavelet Transform, International Journal of Computer Applications, 50, 12, Page Nos -6-13, 2012.
P. Saha, A.Banerjee and A.Dandapat, Low power and High Speed Factorial Design in 22nm Technology, Int. Conf. on Nanomaterials and Nanotechnology, January 2010, Guwahati, Page Nos -294-301, 2010.
P. Saha, A. Banerjee, I. Banerjee and A. Dandapat, High Speed Low Power Floating Point Multiplier Design Based on CSD (Canonical Sign Digit), VDAT, July 2010, Chandigarh, Page Nos -67-76, 2010.
P. Saha, A. Banerjee, P. Bhattacharyya, A. Dandapat, High Speed ASIC Design of Complex Multiplier Using Vedic Mathematics, IEEE, Techsym, February 2011, Kharagpur, Page Nos -237-241, 2011.
P. Saha, A. Banerjee, P. Bhattacharyya, A. Dandapat, Vedic Divider: Novel Architecture (ASIC) for High Speed VLSI Applications, IEEE, Int. Symp. on Electronic System Design, December 2011, Calicut, Page Nos -67-71, 2011.
P. Saha, A. Banerjee, A. Dandapat, P. Bhattacharyya, Design of High Speed Vedic Multiplier for Decimal Number System, IEEE Symp. on VLSI Design and Test, July 2012, Shibpur, Page Nos -79-88, 2012.
P. Saha, D. Kumar, P. Bhattacharyya, A. Dandapat, ASIC Implementation of High Speed Processor for Computing Fast Hartley Transformation, IEEE Conf. on Advanced Electronics System, September 2013, Pilani, Page Nos -334-336, 2013.
P. Saha, D. Kumar, P. Bhattacharyya, A. Dandapat, Reciprocal unit based on Vedic mathematics for signal processing applications, IEEE Symp. on Electronic System Design, December 2013, Singapore, Page Nos -41-45, 2013.
P. Saha, A. Banerjee, and A. Dandapat, High Speed Low Power Complex Multiplier Design Using Parallel Adders and Subtractors, Int. J. on Electronic and Electrical Engineering, 7, 11, Page Nos -8-46, 2009.
P. Saha, A. Banerjee, A. Dandapat, and P. Bhattacharyya, Vedic Mathematics Based 32-Bit Multiplier Design for High Speed Low Power Processor, Int. J. of Smart Sensing and Intelligent System, 4, 2, Page Nos -268-284, 2011.
P. Saha, A. Banerjee, A. Dandapat, and P.Bhattacharyya, ASIC Implementation of High Speed Processor for Calculating Discrete Fourier Transformation using Circular Convolution Technique, Int. J. of World Scientific and Engineering Academy and Society (WSEAS), 10, 8, Page Nos -278-288, 2011.
P. Saha, A. Banerjee, A. Dandapat, and P.Bhattacharyya, ASIC Design of a High Speed Low Power Circuit for Calculation of Factorial of 4-Bit Numbers Based on Ancient Vedic Mathematics, Microelectronics Journal (Elsevier), 42, 12, Page Nos -1343-1352, 2011.
P. Saha, A. Banerjee, A. Dandapat, and P.Bhattacharyya, A High Speed Multiplier using High Accuracy Floating Point Logarithmic Number System, Computer Science & Engineering and Electrical Engineering, Scientia Iranica, 22, 3, Page Nos -826-841, 2013.
P. Saha, P. Bhattacharyya, and A. Dandapat, Improved Floating Point Multiplier Design Based on Canonical Sign Digit, Int. J. of Technology, 5, 1, Page Nos -22-31, 2014.
P. Saha, A. Banerjee, P.Bhattacharyya, and A. Dandapat, Improved Matrix Multiplier Design for High Speed DSP Applications, IET Circuits Devices and Systems, 8, 1, Page Nos -27-37, 2014.
P. Saha, D. Kumar, P. Bhattacharyya, and A. Dandapat, Vedic Division Methodology for High Speed VLSI Applications, Journal of Engineering, IET, 1, Page Nos -1-7, 2014.
P. Saha, D. Kumar, P. Bhattacharyya, and A. Dandapat, Design of 64-bit squarer based on Vedic mathematics, Journal circuit systems and computers, 22, 7, Page Nos -1450092- 1-19, 2014.
Rangababu Peesapati, FPGA based System on Chip (SoC) for Space computation, Planex Newsletter, 6, 1, Page Nos -16-20, 2016. https://www.prl.res.in/~rajiv/planexnews/newarticles/Volume%20-6,%20Issue-1.17-21.pdf
P.Rangababu, S.L Sabat, and K.Venu, Automatic IP Core generation in SoC, Letters in International Journal of Recent Trends in Engineering, 2, Page Nos -92-94, 2009. http://searchdl.org/public/journals/2009/IJRTET/2/6/349.pdf
D.Ajaykumar, Samrat L.Sabat,P.Rangababu, Reliable High Speed Data Acquisition System using FPGA, In Proceedings of Second International Conference on Emerging Trends in Engineering & Technology(ICETET), 16-18 Dec, Nagpur, Page Nos -392 - 396, 2010.
S.L.Sabat, Shravan Kumar, P. Rangababu, Differential Evolution Algorithm for Motion Estimation, Multi-disciplinary Trends in Artificial Intelligence, 7-9 Dec, Hyderabad, Page Nos -309-316, 2011.
S.L.Sabat, P.Rangababu, K.P.Karthik, System on chip implementation of 1-D Wavelet transform based denoising of Fiber Optic Gyroscope signal on FPGA, In Proceedings of IEEE Annual India Conference: Engineering Sustainable Solutions, INDICON, 16-18 Dec, Hyderabad, Page Nos -1 - 5, 2011.
K.P.Karthik, P.Rangababu,S.L Sabat and J. Nayak, System on Chip implementation of Adaptive moving average based multiple-model Kalman filter for denoising Fiber Optic Gyroscope signal, In Proceedings of International Symposium on Electronic System Design (ISED), 19-21 Dec, Kochi, Page Nos -170 - 175, 2011.
M. Narasimhappa, S.L Sabat, P Rangababu, J Nayak, An improved adaptive Kalman Filter for denoising fiber optic gyro drift signal, In Proceedings of IEEE Annual India Conference: Engineering Sustainable Solutions (INDICON), 13-15 Dec, Mumbai, Page Nos -1 - 6, 2013.
M.Narasimhappa, P.Rangabab, S.L.Sabat, J. Nayak, A modified Sage-Husa adaptive Kalman Filter for denoising fiber optic gyroscope signal, In Proceedings of IEEE Annual India Conference: Engineering Sustainable Solutions (INDICON), 7-9 Dec, Kochi, Page Nos -1266-1271, 2012.
Rangababu Peesapati, K. Shravan Kumar, and Samrat L. Sabat, FPGA based Fiber Optic Gyroscope signal Denoising using Discrete Wavelet Transform, International Journal of Engineering & Applied Sciences, 7, 11, Page Nos -1480-1489, 2012.
Kiran Kumar Anumandla,Rangababu Peesapati, Samrat L. Sabat and Siba K. Udgata, SoC based floating point implementation of differential evolution algorithm using FPGA, International Journal of Design Automation and Embedded Systems, Springer, 16, 4, Page Nos -221-240, 2012.
Kiran Kumar Anumandla, Rangababu Peesapati,Samrat L. Sabat, Field Programmable Gate Array Implementation of Spectrum Allocation technique for Cognitive Radio Networks, International Journal of Computer and Electrical Engineering, Elsevier, 42, Page Nos -178-192, 2015.
Kiran Kumar Anumandla,Rangababu Peesapati, Samrat L. Sabat, Siba K. Udgata and Ajith Abraham, FGPA based Differential Evolution Coprocessor: A case study of spectrum allocation in cognitive radio network, nternational Journal of Computer and Digital Techniques IET, 7, 5, Page Nos -221-234, 2013.
Narasimhappa Mundla, Samrat L. Sabat, Rangababu Peesapati, and J.Nayak,, An innovation based random weighting estimation mechanism for denoising fiber optic gyro drift signal, International Journal of International Journal for Light and Electron Optics (OPTIK) Elsevier, 125, 3, Page Nos -1192-1198, 2014.
Satabdy Jena, Gayadhar Panda, Rangababu Peesapati, Real-time Analysis and Simulation of Multi-String Grid Connected Photovoltaic Inverter using FPGA, In Proceedings of 6th IEEE International Conference on Power Systems (ICPS), 4-6 March 2016, Delhi, Page Nos -1-6, 2016.
R. Ganesh, Gayadhar Panda, Rangababu Peesapati, Hardware-In-Loop Implementation of An Adaptive Droop Control Strategy for Effective Load Sharing in a Dc Microgrid, In Proceedings of 6th IEEE International Conference on Power Systems (ICPS), 4-6 March 2016, Delhi, Page Nos -1-6, 2016.
Ch.V.Rama Rao, M.B.Rama Murthy and K.Srinivasa Rao, Speech enhancement using modified Wiener filter, National Conference, FACE 09, March 19-21, Hyderabad, Page Nos -1-4, 2009.
Ch.V.Rama Rao, M.B.Rama Murthy and K.Srinivasa Rao, Speech enhancement using crosscorrelation compensated multi-band Wiener filter combined with constrained perceptual weighting filter, IEEE Technically Sponsored National Conference on Emerging Trends and Applications in Computer Science (NCETACS-2011), March 4-5, Shillong, Page Nos -1-6, 2011. ieeexplore.ieee.org/xpls/abs_all.jsp?arnumber=5751399
Ch.V.Rama Rao, M.B.Rama Murthy and K.Srinivasa Rao, Speech enhancement using modified Wiener filter, National Conference, FACE 09, March 19-21, Hyderabad, Page Nos -1-4, 2009.
Ch.V.Rama Rao, M.B.Rama Murthy and K.Srinivasa Rao, Speech enhancement using crosscorrelation compensated multi-band Wiener filter combined with constrained perceptual weighting filter, IEEE Technically Sponsored National Conference on Emerging Trends and Applications in Computer Science (NCETACS-2011), March 4-5, Shillong, Page Nos -1-6, 2011. ieeexplore.ieee.org/xpls/abs_all.jsp?arnumber=5751399
Ch.V.Rama Rao, K.Anitha Sheela, K.Satya Prasad and A.V.N.Tilak, A noise reduction pre-processor for mobile voice communication using perceptually weighted spectral subtraction method, 3rd International Conference ObCom-2006, December 16-19, Vellore, Tamilnadu, Page Nos -91-100, 2006. www.abebooks.com/...3rd-International-Conference-Obcom--2006.../plp
Ch.V.Rama Rao, and M.B.Ramamurthy, A new approach for improved performance of hands- free phones, TIES-2007, November 12-14, Chennai, Page Nos -66-68, 2007. www.sathyabamauniversity.ac.in/sitepagetwo.php?firstref=149...67
Ch.V.Rama Rao, K.Anitha Sheela, M.B.Ramamurthy and A.V.N.Tilak, Speech enhancement in non-stationary noise environments- a new approach, International Conference on RF and Signal Processing Systems, February 1-2, Vaddeswaram, Guntur, Andhra Pradesh, Page Nos -262-265, 2008. www.kluniversity.in/ece/pdf/20081.pdf
Ch.V.Rama Rao, M.B.Rama Murthy and K.Anitha Sheela, A new technique for street noise reduction in signal processing applications, TENCON 2008, November 19-21, Hyderabad, Page Nos -1-5, 2008. ieeexplore.ieee.org/xpls/abs_all.jsp?arnumber=4766755
Ch.V.Rama Rao, M.B.Rama Murthy and K.Srinivasa Rao, A modified Wiener filter combined with perceptual weighting for speech enhancement, International Conference on Intelligent Human Computer Interaction, January 16-18, Alahbad, Page Nos -205-211, 2010. www.springer.com/in/book/9788132201335
Ch.V.Rama Rao, Gowthami.A, Harsha.D, Rajkumar.L, M.B.Rama Murhty, K. Srinivasa Rao and K.Anitha Sheela, Noise estimation for speech enhancement in non-stationary environments- a new method, International Conference on Signal and Image Processing, ICSIP, World Academy of Science, Engineering and Technology, August 25-27, Singapore, Page Nos -36-38, 2010. waset.org/publication/
Vargil Vijay. E, Ch.V. Rama Rao, G.N. Swamy and M. Kamaraju, Electronic Control Unit for an Adaptive Cruise Control System in a Car Using Electronic Fuel Injection, Int. Conference on Next Generation Communication and Computing Systems ( ICNGC2S-10), December 25-26, Chandigarh, Page Nos -191-193, 2010. http://www.ietan.org/icngc2s10/icngc2s10.html
Vargil Vijay. E, Ch.V. Rama Rao, Vargil Kumar. E and G.N. Swamy, Electronic Control Unit for an Adaptive Cruise Control System and Engine Management System in A Vehicle Using Electronic Fuel Injection, Int. Conference on Emerging Trends in Robotics and Communication Technologies (INTERACT-2010), December 3-5, Chennai, Page Nos -143-146, 2010. http://ieeexplore.ieee.org/stamp/stamp.jsp?arnumber=5706213
M.Priyanka, Ch.V.Rama Rao, Speech enhancement using self adaptive Wiener filter based on hybrid apriori SNR, Int. Conference on Nanoscience, Engineering & Advanced Computing (ICNEAC-2011), July 8-10, Narsapur, Andhra Pradesh, Page Nos -498-502, 2011.
Ch.V.Rama Rao, M.B.Rama Murthy and K.Srinivasa Rao, Speech Enhancement Using Perceptual Wiener Filter Combined with Unvoiced Speech – A New Scheme, RAICS-2011, September 22-24, Trivandrum, Page Nos -688-691, 2011. http://ieeexplore.ieee.org/xpl/articleDetails.jsp?reload=true&arnumber=6069398
T.Muni Kumar, Ch.V.Rama Rao, M.B.Rama Murthy and K.Srinivasa Rao, A New Speech Enhancement Technique Using Perceptual Constrained Spectral Weighting Factors, Int. Conference on Electronics and Communication Engineering, October 1-3, Bangalore, Page Nos -191-195, 2011. scholar.google.co.in/citations?user=CIw0vqMAAAAJ&hl=en
Ch.V.Rama Rao, M.B.Rama Murthy and K.Srinivasa Rao, A Novel Two Stage Single Channel Speech Enhancement Technique, INDICON 2011, December 16-18, Hyderabad, Page Nos -1-5, 2011. http://ieeexplore.ieee.org/xpls/abs_all.jsp?arnumber=6139375&tag=1
N.Srisakthi, Rama Rao.Ch.V and Vidya.M, Implementation of code synchronization for CDMA applications using recursive digital matched filter, IEEE International Conference on Communication and Signal Processing-ICCSP'2014, April 3-5, Tamilnadu, Page Nos -1223-1227, 2014. ieeexplore.ieee.org/xpls/abs_all.jsp?arnumber=6950046
Avadhesh Kumar, Ch V Rama Rao, Low-power structures of digital matched filter for direct sequence spread spectrum systems, IEEE WISPNET 2016, March 23-25, Chennai, Page Nos -263-268, 2016. http://ieeexplore.ieee.org/stamp/stamp.jsp?arnumber=7566134
V. Kumar,K.L.Baishnab, A Comparative Analysis Of CCD And CMOS Image Sensors Technology, International Journal Of Technological Advancement & Research(IJTAR), 3, 4, Page Nos -320-322, 2013.
V. Kumar,K.L.Baishnab, A Comparative Analysis Of CCD And CMOS Image Sensors Technology, International Conference On Technological Advancement & Research, December, Goa, India, 2013.
V. Kumar and A. Dandapat, Transistor Level Implementation of Cyclic Combinational Circuits, International Conference on Advances in Communication, Network, and Computing – CNC 2014, Febraury, Chennai, India, 2014.
V. Kumar, Md. A. Laskar, Y. Singh,S. Majumdar and S. K. Sarkar, ANN Based Adaptive Detection of ECG Features from Respiratory, Pleythsmographic and ABP Signals, 3rd International Conference on Frontiers in Intelligent Computing Theory & Application (FICTA-2014), November, Bhubaneswar,Odissa,India, Page Nos -359-365, 2014. https://link.springer.com/chapter/10.1007/978-3-319-11933-5_39
V. Kumar, C. K. Jha, G. Thapa and A. Dandapat, Design of Low Power and High Speed Carry Look Ahead Adder (CLA) Using Hybrid CMOS Logic Style, International Conference on Micro Electronics Electromagnetics and Telecommunications ( ICMEET 2015), December, Visakhapatnam, Andhra Pradesh, India, Page Nos -645-654, 2015. https://link.springer.com/chapter/10.1007/978-81-322-2728-1_61
V. Kumar, B. Kumar, Performance Analysis Of Optical Communication Receivers Employing Second Harmonic Generation Effect Of Quantum Dots With Different Confinements, International Journal of Engineering Research & Technology (IJERT), 2, 10, Page Nos -3457-3461, 2013. http://www.ijert.org/view-pdf/6027/performance-analysis-of-optical-communication-receivers-employing-second-harmonic-generation-effect-of-quantum-dots-with-different-confinements
P. Bhattacharyya, B. Kundu, S. Ghosh, V. Kumar and A. Dandapat, Performance Analysis of a Low Power High Speed Hybrid 1 Bit Full Adder Circuit, IEEE Transactions on Very Large Scale Integration Systems, 23, 10, Page Nos -2001-2008, 2015. dx.doi.org/10.1109/TVLSI.2014.2357057
Rangababu Peesapati, Samrat L. Sabat, K.P. Karthik, M. Narasimhappa, N. Giribabu, and J. Nayak, FPGA-based Embedded Platform for Fiber Optic Gyroscope Signal Denoising, International Journal of Circuit Theory and Applications, Willey Blackwell, 42, 7, Page Nos -744–757, 2014.
Rangababu Peesapati, Samrat L. Sabat, K.P. Karthik, N. Giribabu and J. Nayak, Efficient Hybrid Kalman Filter for denoising Fiber Optic Gyroscope Signal, International Journal for Light and Electron Optics (OPTIK),Elsevier, 124, 20, Page Nos -4549–4556, 2013.
Rangababu Peesapati, Kiran kumar Anumandla, Samrat L. Sabat, Comparative Study of System on Chip based solution for Floating and Fixed point Differential Evolution algorithm, International Journal of Swarm and Evolutionary Computation,Elsevier, 19, Page Nos -68-81, 2014.
Rangababu Peesapati, Samrat L. Sabat, Kiran Kumar Anumandla, Palani Karthik Kandyala, and Nayak Jagnnath, FPGA based Embedded Co-Processor for Real time Fiber Optic Gyroscope signal denoising, International Journal of Digital Signal Processing, Elsevier, 23, 5, Page Nos -1813-1825, 2013.
Ch.V.Rama Rao, M.B.Rama Murthy and K.Srinivasa Rao, Speech enhancement in non-stationary noise environments: an efficient approach, The Icfai University Journal of Telecommunications, 1, 2, Page Nos -24-31, 2009. scholar.google.co.in/citations?user=CIw0vqMAAAAJ&hl=en
Ch.V.Rama Rao, M.B.Rama Murthy and K.Srinivasa Rao, A perceptual approach to reduce musical noise using critical bands tonality coefficients and masking thresholds, Int. Journal of Communications, Network and System Sciences, 2, 8, Page Nos -742-745, 2009. www.scirp.org/journal/PaperInformation.aspx?PaperID=822
Ch.V.Rama Rao, Gowthami.A, Harsha.D, Rajkumar.L, M.B.Rama Murhty, K. Srinivasa Rao and K.Anitha Sheela, Noise estimation for speech enhancement in non-stationary environments-a new method, Journal of World Academy of Science, Engineering and Technology, 1, 70, Page Nos -739-742, 2010. waset.org/.../noise-estimation-for-speech-enhancement-in-non-stationary...
Ch.V.Rama Rao, M.B.Rama Murthy and K.Srinivasa Rao, Speech Enhancement Using a Modified Apriori SNR and Adaptive Spectral Gain Control, Int. Journal of Computer Applications, 12, 12, Page Nos -13-17, 2011. www.scilit.net/journals/14936/14700/10/Newest
Ch.V.Rama Rao, M.B.Rama Murthy and K.Srinivasa Rao, Noise Reduction Using mel-scale Spectral Subtraction with Perceptually Defined Subtraction Parameters-A New Scheme, Signal & Image Processing: An International Journal, 2, 1, Page Nos -135-149, 2011. www.scilit.net/journals/17233/260/10/Newest
Ch.V.Rama Rao, M.B.Rama Murthy and K.Srinivasa Rao, Speech Enhancement Using Cross-Correlation Compensated Multi-Band Wiener Filter Combined with Harmonic Regeneration, Journal of Signal and Information Processing, 2, 2, Page Nos -117-124, 2011. scholar.google.co.in/citations?user=CIw0vqMAAAAJ&hl=en
Ch.V.Rama Rao, M.B.Rama Murthy and K.Srinivasa Rao, Speech Enhancement Using Sub-band Cross-correlation Compensated Wiener Filter Combined with Harmonic Regeneration, International Journal of Electronics and Communications, Elsevier publications, 66, 6, Page Nos -459-464, 2012. https://www.infona.pl/.../bwmeta1.element.elsevier-8803733b-4de1-36cf..
T.Muni Kumar, Ch.V.Rama Rao, M.B.Rama Murthy and K.Srinivasa Rao, A New Speech Enhancement Technique Using Perceptual Constrained Spectral Weighting Factors, International Journal of Electronics Signals and Systems, 1, 2, Page Nos -30-35, 2012. scholar.google.co.in/citations?user=CIw0vqMAAAAJ&hl=en
Srisakthi.N, Ch.V.Rama Rao and M.Vidya, Implementation of CDMA receiver using recursive digital matched filter, IOSR Journal of VLSI and Signal Processing (IOSR-JVSP), 4, 3, Page Nos -23-28, 2014. iosrjournals.org/iosr-jvlsi/papers/vol4-issue3/Version-2/D04322328.pdf
A. Sarkhel, S. R. B. Chaudhuri, Design of a compact triple-band metamaterial absorber with wide angle of incidence using connected resonator topology, International Conference on Electromagnetics in Advanced Applications (ICEAA), September 7-11, Turin,Italy, 2015.
A. Sarkhel, D. Mitra, and S. R. B. Chaudhuri, A Compact Metamaterial with Multi-band Negative-index Characteristics, Springer: Applied Physics A, 122, 4, Page Nos -122:471, 2016.
D. Mitra, B. Ghosh, A. Sarkhel, and S. R. B. Chaudhuri, A Miniaturized Ring Slot Antenna Design With Enhanced Radiation Characteristics, IEEE Transactions on Antennas And Propagation, 64, 1, Page Nos -300–305, 2015.
A. Sarkhel, D. Mitra, S. Paul, and S. R. B. Chaudhuri, A Compact Meta-Atom for Dual Band Negative Permittivity Metamaterial, Wiley: Microwave and Optical Technology Letters, 57, 5, Page Nos -1152–1156, 2015.
D. Mitra, A. Sarkhel, O. Kundu, and S. R. B. Chaudhuri, Design of Compact and High Directive Slot AntennasUsing Grounded Metamaterial Slab, IEEE Antenna & Wireless Propagation Letters, 14, Page Nos -811–814, 2014.
M. Chanda, A. Dandapat, H. Rahaman, Implementation of Ultra Low-Power 8 bit CLA using Single Phase Adiabatic Dynamic Logic, Advances in Recent technologies in Communication and Computing (ARTCOM 2010), -, Kerala, Page Nos --, 2010.
M. Chanda, R. Mitra, P. Sil, A. Dandapat and H. Rahaman, Comparative analysis of Adiabatic compressor circuits for ultra low power DSP application, Advances in Recent technologies in Communication and Computing (ARTCOM 2010), -, Kerala, Page Nos --, 2010.
B. Ghosh, A. Dandapat, Design of Combinational Circuits by Cyclic Combinational Method for Low Power VLSI, International Symposium on Electronic System Design (ISED 2010), Dec, Bhubaneswar, Orissa, Page Nos --, 2010.
P. K. Saha, A. Banerjee, A. Dandapat, High Speed Low Power Floating Point Multiplier Design Based on CSD (Canonical Sign Digit), 14th VLSI Design And Test Symposium (VDAT 2010), Jul, -, Page Nos --, 2010.
P. Saha, A. Banerjee, P. Bhattacharyya, A. Dandapat, High Speed ASIC Design of Complex Multiplier Using Vedic Mathematics, Proceedings of the IEEE, Techsym, -, -, Page Nos --, 2011.
M. Chanda, A. Dandapat, H. Rahaman, Design and Analysis of Tree-Multiplier using Single-Clocked Energy Efficient Adiabatic Logic, Proceedings of the IEEE, Techsym, -, -, Page Nos --, 2011.
P. Saha, A. Banerjee, P. Bhattacharyya and A. Dandapat, Vedic Divider: Novel Architecture (ASIC) for High Speed VLSI Applications, International Symposium on Electronic System Design (ISED), Dec, Kochi, India, Page Nos --, 2011.
M. Chanda, A. Dandapat, H. Rahaman, Pre-Settable Single Clocked Adiabatic Sequential Circuits for Ultra Low Power Architectures, 9th international conference on power electronics and Drive systems, -, -, Page Nos --, 2011.
P. Saha, A. Banerjee, A. Dandapat and P. Bhattacharyya, Design of High Speed Vedic Multiplier for Decimal Number System, VLSI Design & Test Symposium, -, -, Page Nos --, 2012.
P. Saha, D. Kumar, P. Bhattacharyya and A. Dandapat, Reciprocal unit based on Vedic mathematics for signal processing applications, International Symposium on Electronic System Design (ISED), Dec, Singapore, Page Nos --, 2013.
P. Saha, P. Bhattacharyya, D. Kumar and A. Dandapat, ASIC Implementation of High Speed Processor for Computing Fast Hartley Transformation, International Conference on Advanced Electronic Systems, Sep, CSIR-CEERI Pilani, Page Nos --, 2013.
V. Kumar and A. Dandapat, Transistor Level Implementation of Cyclic Combinational Circuits, International Conference on Advances in Communication, Network, and Computing – CNC 2014, Feb, Chennai, India, Page Nos --, 2014.
V. Kumar, C. K. Jha, G. Thapa and A. Dandapat, Design of Low Power and High Speed Carry Look Ahead Adder (CLA) Using Hybrid CMOS Logic Style, International Conference on Micro Electronics Electromagnetics and Telecommunications ( ICMEET 2015), Dec, Visakhapatnam, Andhra Pradesh, India, Page Nos --, 2015.
S. Mukherjee, P. Mustafa, D. Kayal, A. Dandapat and C. K. Sarkar, Flash Type ADC Using Input Voltage Level Based Circuit Activation Technique, International Journal of Electronics & Telecommunication And Instrumentation Engineering, 6, 1, Page Nos -7, 2011.
P. Saha, A. Dandapat, P. Bhattacharrya, ASIC Implementation of High Speed Processor for Calculating Discrete Fourier Transformation using Circular Convolution Technique, WSEAS Trans. on Circuits and Systems, 8, 10, Page Nos -278?288, 2011.
P. Saha, A. Dandapat, P. Bhattacharrya, ASIC Design of a High Speed Low Power Circuit for Factorial Calculation Using Ancient Vedic Mathematics, Microelectronics Journal, 42, ?, Page Nos -1343?1352, 2011.
M. Chanda, A. S. Chakraborty, A. Dandapat and H. Rahaman, Pre-settable sequential circuits design using single-clocked energy efficient adiabatic logic, Journal of Electron Devices, 12, ?, Page Nos -6, 2012.
D. Kayal, A. Dandapat, Design of a High Performance Memory Using a Novel Architecture of Double Bit CAM and SRAM, International Journal of Electronics, Tailor & Francis, 99, 12, Page Nos -1691?1702, 2012.
P. Saha, A. Banerjee, P. Bhattacharyya, A. Dandapat, A High Speed Multiplier using High Accuracy Floating Point Logarithmic Number System, Trans. on Computer Sc. & Engineering & Electrical Engineering, Science and Technology, Scientia Iranica, 21, 3, Page Nos -15, 2013.
D. Ghosh, P. C. Mondal, D. Kayal, P. Bhattacharyya, A. Dandapat, A Novel Design of Seven Segment Decoder using Cyclic Combinational Technique, International Journal of Low Power Electronics, ASP, 9, 4, Page Nos -421?426, 2013.
D. Kayal, P. Mostafa, A. Dandapat, C. K. Sarkar, Design of High Performance 8 bit Multiplier using Vedic Multiplication Algorithm with McCMOS Technique, Journal of Signal Processing Systems, Springer, 76, 1, Page Nos -1?9, 2014.
P. Saha, P. Bhattacharyya, A. Dandapat, Improved floating point multiplier design based on canonical sign digit, International journal of Technology, 5, 1, Page Nos -9, 2014.
P. Saha, D. Kumar, P. Bhattacharyya, A. Dandapat, Vedic Division Methodology for High Speed VLSI Applications, IET Journal of Engineering, ?, ?, Page Nos -9, 2014.
P. Saha, D. Kumar, P. Bhattacharyya, A. Dandapat, Design of 64-Bit Squarer Based On Vedic Mathematics, Journal of Circuits, Systems, and Computers, World Scientific, 23, ?, Page Nos -19, 2014. dx.doi.org/10.1142/S0218126614500923
P. Bhattacharyya, B. Kundu, S. Ghosh, V. Kumar, and A. Dandapat, Performance Analysis of a Low Power High Speed Hybrid 1 Bit Full Adder Circuit, IEEE Transactions on Very Large Scale Integration Systems, 23, 10, Page Nos -2001?2008, 2015. dx.doi.org/10.1109/TVLSI.2014.2357057
S. Mishra and A. Dandapat, EMDBAM: A Low Power Dual Bit Associative Memory with Match Error and Mask Control, IEEE Transactions on Very Large Scale Integration Systems, 24, 6, Page Nos -2142?2151, 2016. dx.doi.org/10.1109/TVLSI.2015.2503005
V. Kumar, C. K. Jha, G. Thapa, and A. Dandapat, A Novel Methodology for Design of Cyclic Combinational Circuits, Journal of Low Power Electronics, 12, ?, Page Nos -1?13, 2016.
V. Kumar and A. Dandapat, Design Methodology for Multiple Output Combinational Circuits Using Cyclic Combinational Technique, Journal of Circuits, Systems, and Computers, 25, 12, Page Nos -1?20, 2016.
S. Mishra, T. V. Mahendra, and A. Dandapat, A 9-T 833-MHz 1.72-fJ/bit/search quasi static ternary fully associative cache tag with selective matchline evaluation for wire speed applications, IEEE Transactions on Circuits and Systems I: Regular Papers, 63, 11, Page Nos -1910-1920, 2016. dx.doi.org/10.1109/TCSI.2016.2592182
