•     Ph.D from IIEST 
•     M. Tech from Tezpur University 
•     
  

International Journals:

 29.       R. U. Ahmed, E.A. Vijaykumar, and P. Saha, “Sensitivity Analysis of the UTBSOI Transistor based Two-Stage              Operational Transconductance Amplifier”, Electronics Journal, vol. 24, no. 2, pp. 75-80, Dec. 2020 .

28.      S.D. Thabah, and P. Saha, “Improved Signed Binary Multiplier Through New Partial Product Generation Scheme” Journal of Circuits, Systems and Computers, vol. 29, no. 16, 2150162-1-21, 2021.

27.     S. K. Beura, A. A. Jawale, B. P. Devi, and P. Saha, “On the Implementation of Multi-bit Inexact Adder Cells and Application towards Image De-noising”, Electronics Journal, vol. 24, no. 1, pp. 35-44, 2020.

26.     S.D. Thabah, and P. Saha, “A Low Quantum Cost Implementation of Reversible Binary-Coded-Decimal Adder”, Periodica Polytechnica Electrical Engineering and Computer Science, vol. 64, no. 4, pp. 343-351, 2020.

25.       R.U. Ahmed, E.A. Vijaykumar, H.S. Ponakala, M. Y. V. Balaji, and P. Saha, “Design of double-gate CMOS based two-stage operational transconductance amplifier using the UTBSOI transistors” U.P.B. Sci. Bull., Series C, vol. 82, no. 2, pp. 173-188, 2020.

24.        R. U. Ahamed, and P. Saha, “Revisiting Analytical Models of N-Type Symmetric Double-Gate MOSFETs”, Electronics Journal, vol. 24, no. 1, pp. 17-34, 2020.

23.    S. D. Thabah, M. Sonowal, R. U. Ahmed, and P. Saha, “Fast and Area Efficient Implementation of RSA Algorithm”,             Procedia Computer Science, vol. 165, pp. 525-531, 2019.

             22.     R. U. Ahamed, S.D. Thabah, and P. Saha, “Design of New Multi-Column 5,5:4 Compressor Circuit Based on Double-                   Gate UTBSOI Transistors”, Procedia Computer Science, vol. 165, pp. 32-540, 2019.

21.      R. U. Ahamed, and P. Saha, “Implementation Topology of Full Adder Cells”, Procedia Computer Science, vol. 165, pp. 676-683, 2019.

20.      R. U. Ahamed, and P. Saha, “Modeling of Short P-Channel Symmetric Double-Gate MOSFET for Low Power Circuit Simulation”, Periodica Polytechnica Electrical Engineering and Computer Science, vol. 64, no. 1, pp. 106-114, 2020.

19.      S. D. Thabaha, and P. Saha, “Low Quantum Cost Realization of Reversible Binary-Coded-Decimal Adder”, Procedia Computer Science, Accepted, 2019.

18.       R. U. Ahamed, E. A. Vijaykumar, and P. Saha, “Single-Stage Operational Transconductance Amplifier Design based on gm/Id Methodology” Electronics Journal, vol. 23, no. 2, pp. 52-59, 2019.

17.       S.D. Thabah, and P. Saha, “New Design Approaches of Reversible BCD Encoder using Peres and Feynman Gates” ICT Express, vol. 6, no. 1, pp. 38-42, 2020.

16.       P. Saha, and P. Samanta, “Design and Architecture of new 11:2 Decimal Compressors” Sadhana, vol. 44, no. 5, 125(1-12), 2019

15.       S.D. Thabah, M. Sonowal, and P. Saha, “On the Design of Efficient Residue-to-Binary Converters” Procedia Computer Science, vol. 132, pp. 816-823, 2018.

14.       D. Kumar, P. Saha, and A. Dandapat, “Vedic Algorithm for Cubic Computation and VLSI Implementation” Engineering Science and Technology, an International Journal (Elsevier), Vol.  20, no. 5, pp. 1494-1499, Oct. 2017.

13.       D. Kumar, P. Saha, and A. Dandapat, “Hardware implementation methodologies of fixed point division algorithms” Int. J. of Smart Sensing and Intelligent System, vol. 10, no. 3, pp. 630-645, Sept. 2017.

12.       S.D. Thabah, M. Sonowal, and P. Saha, “Experimental Studies on Multi Operand Adders” Int. J. of Smart Sensing and Intelligent System, vol. 10, no. 2, 2017,  pp. 327-340, June 2017.

11.     A. Shadap, P. Saha, “Discrete Fourier transformation processor based on complex radix (1 + j) number system”, Engineering Science and Technology, an International Journal(Elsevier), Vol. 20, no. 1, pp. 80-88, Feb. 2017.

10.     P. Saha, D. Kumar “A new algorithm for the Computation of the Decimals of the Inverse,” Computer Science & Engineering and Electrical Engineering, Scientia Iranica, vol. 24, no. 3, 1363-1372, 2017.

9.         P. Saha, D. Kumar, P. Bhattacharyya, and A. Dandapat, “Design of 64-bit squarer based on Vedic mathematics,” Journal circuit systems and computers, vol. 22, no. 7, 2014, pp. 1450092- 1-19.

8.         P. Saha, P. Bhattacharyya, and A. Dandapat, “Improved Floating Point Multiplier Design Based on Canonical Sign Digit”, Int. J. of Technology, vol. 5, no. 1, 2014, pp. pp. 22-31.

7.         P. Saha, D. Kumar, P. Bhattacharyya, and A. Dandapat, “Vedic Division Methodology for High Speed VLSI Applications”, Journal of Engineering, IET, Vol. 2014, No. 2, 2014, pp. 51-59

6.         P. Saha, A. Banerjee, A. Dandapat, and P. Bhattacharyya, “A High Speed Multiplier using High Accuracy Floating Point Logarithmic Number System”, Computer Science & Engineering and Electrical Engineering, Scientia Iranica, vol. 21, no. 3, 2013, pp.  826-841.

5.         P. Saha, A. Banerjee, P. Bhattacharyya, and A. Dandapat, “Improved Matrix Multiplier Design for High Speed DSP Applications”, IET Circuits Devices and Systems, vol. 8, no. 1, pp. 27-37, Jan 2014.

4.         P. Saha, A. Banerjee, A. Dandapat, and P. Bhattacharyya, “ASIC Design of a High Speed Low Power Circuit for Calculation of Factorial of 4-Bit Numbers Based on Ancient Vedic Mathematics”, Microelectronics Journal (Elsevier), vol. 42, no. 12, 2011, pp. 1343-1352, Dec. 2011.

3.         P. Saha, A. Banerjee, A. Dandapat, and  P.Bhattacharyya, “ASIC Implementation of High Speed Processor for Calculating Discrete Fourier Transformation using Circular Convolution Technique”, Int. J. of World Scientific and Engineering Academy and Society (WSEAS), vol. 10, no. 8, pp. 278-288, Aug. 2011. (ISSN: 1109-2734).

2.         P. Saha, A. Banerjee, A. Dandapat, and P. Bhattacharyya, “Vedic Mathematics Based 32-Bit Multiplier Design for High Speed Low Power Processor”, Int. J. of Smart Sensing and Intelligent System, vol. 4, no. 2, 2011,  pp. 268-284, June 2011. (ISSN: 1178-5608).

1.         P. Saha, A. Banerjee, and A. Dandapat, “High Speed Low Power Complex Multiplier Design Using Parallel Adders and Subtractors”,  Int. J. on Electronic and Electrical Engineering, (IJEEE),vol. 07, no. 11, 2009,  pp. 38-46, Nov.  2009. (ISSN: 0974-2042).

Book Chapter:

4.         M. Roy, A. Das, B. Neogi, and P. Saha, “Healthcare 4.0 in Prospective of Respiratory support system and Artificial Lung”, Intelligent Interactive Multimedia Systems for e-Healthcare Applications, Apple Academic Press, Accepted 2020.

3.         R. Ahmed, and P. Saha, “Power and Delay Comparison of 7:3 Compressor Designs Based on Different Architectures of XOR Gate” G. Ranganathan et al. (eds.), Inventive Communication and Computational Technologies, vol. 89, pp. 461-469.  https://doi.org/10.1007/978-981-15-0146-3_44

2.    R. Ahmed and P. Saha, “Implementation Aspects of Multi-bit Adders using UTBSOI Transistors”, Yu-Dong Zhang et. al (eds), Smart Trends in Computing and Communications, vol. 182,  pp. 355-364.

1.        D. Kumar and P. Saha, “Accelerating latency of binary division through Vedic methodology” Yu-Dong Zhang et. al. (eds), Smart Trends in Computing and Communications, vol. 182, pp. 365-378.

Conference proceedings:

14.       P. Saha, R.U. Ahmed, and S. D. Thabah, “Design and Implementation of Multi Operand , , and  Modulo Set Adder”, ICCDN, Accepted 2020.

13.       S. Roy, D. Kumar, A. Dandapat, and P. Saha, “Discretized Sinusoidal Waveform Generators for Signal Processing Applications”, IEEE Int. Conf. on Trends in Electronics and Informatics, pp. 1350-1353, 2018.

12.       D. Phiamphu, P. Saha, “Redesigned the Architecture of Extended-Euclidean Algorithm for Modular Multiplicative Inverse and Jacobi symbol, IEEE Int. Conf. on Trends in Electronics and Informatics, pp. 1345-1349, 2018.

11.       R. Ahmed, P. Saha, “Modeling of Threshold Voltage and Subthreshold Current for P-Channel Symmetric Double-Gate MOSFET in Nanoscale Regime” IEEE Int. Symp. on Nanoelectronic and Information Systems, pp. 179-183, 2017.

10.       P. Saha, P. Samanta, D. Kumar, “4:2 and 5:2 Decimal Compressors,” IEEE Int. Conf. on Intelligent Systems, Modelling and Simulation, pp. 424-429, Jan. 2016.

9.         D. Kumar, A. Sharma, and P. Saha “Integer Division Technique for Signal Processing Applications, Int. Conf. on Ubiquitous Information Management and Communication (ACM), Accepted, 2015.

8.         P. Saha, D. Kumar, and A. Sharma, “Implementation of High Speed Processor for Computing Convolution Sum for DSP Applications, Int. Conf. on Ubiquitous Information Management and Communication (ACM), Accepted, 2015.

7.         P. Saha, D. Kumar, P. Bhattacharyya, A. Dandapat, “Reciprocal unit based on Vedic mathematics for signal processing applications” IEEE Symp. on Electronic System Design, 2013, pp. 41-45.

6.         P. Saha, D. Kumar, P. Bhattacharyya, A. Dandapat, “ASIC Implementation of High Speed Processor for Computing Fast Hartley Transformation”, IEEE Conf. on Advanced Electronics System, 2013, pp. 334-336.

5.         P. Saha, A. Banerjee, A. Dandapat, P. Bhattacharyya, “Design of High Speed Vedic Multiplier for Decimal Number System”, IEEE Symp. on VLSI Design and Testing, VDAT-12, 2012.

4.         P. Saha, A. Banerjee, P. Bhattacharyya, A. Dandapat, “Vedic Divider: Novel Architecture (ASIC) for High Speed VLSI Applications”, IEEE, Int. Symp. on Electronic System Design, pp. 67-71, 2011.

3.         P. Saha, A. Banerjee, P. Bhattacharyya, A. Dandapat, “High Speed ASIC Design of Complex Multiplier Using Vedic Mathematics”, IEEE, Techsym,  pp. 237-241, 2011.

2.         P. Saha, A. Banerjee, I. Banerjee and A. Dandapat, “High Speed Low Power Floating Point Multiplier Design Based on CSD (Canonical Sign Digit)”; IEEE Symp. on VLSI Design and Testing, VDAT-10, 2010.

1.         P. Saha, A.Banerjee and A.Dandapat,“Low power and High Speed Factorial Design in 22nm Technology” in Proc. of the AIP, Int. Conf. on Nanomaterials and Nanotechnology, pp. 294-301, 2010.

Previous/Other Semester/Year

1. Digital Signal Processing , Autumn Semester, 2014
2. Digital Signal Processing , Autumn Semester, 2015
3. VLSI Design, Autumn Semester, 2015
4. Computer Arithmetic , Spring Semester, 2016
5. Digital & Analog Integrated Circuit , Spring Semester, 2016

PhD

M.Tech

B.Tech

• Sneha Choudhury and Lokesh Saini, B.Tech, Complex radix based multiplier, 2015-2016

1. Assistant Professor, NIT Meghalaya, Since 2012
2. Assistant Professor, NIT Meghalaya, January 2012 to May 2012
3. Assistant Professor, JIS College of Engineering, July 2008 to December 2011