prabir.saha@nitm.ac.in
9485177005
https://nitmeghalaya.irins.org/profile/101593
|
Sl. No. |
Title of Project |
Sponsoring
Agency |
Grant Amount |
Period |
Your Role
|
|
|
From |
To |
|||||
|
1 |
UAV Assisted SOIL Moisture Content Determination through 5G
Network |
Department Of Telecommunication Ministry Of Communication |
12670000 |
18-08-2023 To
27-09-2027 |
Principle
Investigator |
|
|
2 |
Development Of On Chip Mems Pressure Sensor Based Tensiometer For
Agriculture |
Ministry Of Electronics And Information Technology |
11098000 |
22-05-2023 To
21-05-2028 |
Principle
Investigator |
|
|
3 |
FIST PROPOSAL |
MINISTRY OF SCIENCE AND TECHNOLOGY |
7500000 |
16-09-2021
to 15-09-2026 |
Principle
Investigator |
|
|
4 |
Visvesvaraya PhD Scheme |
MINISTRY OF ELECTRONICS AND INFORMATION TECHNOLOGY |
6860800 |
18-08-2023
to 17-08-2028 |
Nodal
officer |
|
|
5 |
EFFICIENT HARDWARE ALGORITHM DESIGN FOR CRYPTO PROCESSOR |
TEQIP-III |
199500 |
30-11-2019
to 29-11-2021 |
Principle
Investigator |
|
International Journals:
35. S.K. Beura, S. M. Mahanta, B. P. Devi and P. Saha, “Inexact Radix-4 Booth Multipliers based on New Partial Product Generation Scheme for Image Multiplication”, Integration, The VLSI Journal, Vol. 94, pp. 102096(1-14), 2024.
34. R.U. Ahmed, S.D. Thabah, M. Haque, and P. Saha, “Efficient Modulo Multiplier”, Electronics, Vol. 27, No. 1, pp. 18-24, Jun3 2023.
33. S.D. Thabah, and P. Saha, “Minimizing Ancilla Inputs and Garbage Outputs of Reversible BCD Multiplier”, Journal of Circuits, Systems and Computers, Vol. 31, No. 4, 2250062 (23 pages),2022.
32. P. Saha, and P. Smanta, “Investigations on Decimal Multipliers Through Novel Partial Product Generators”, J. Inst. Eng. India Ser. B, Vol. 103, No. 2, PP. 507-516, April 2022.
31. S. K. Beura, R. U. Ahmed, B. P. Devi, and P. Saha, “On The Implementation of Densely Packed Decimal Number System based Adder: Prospects and Challenges” Electronics Journal, vol. 25, no.1, pp. 20-30. June 2021.
30. S.D. Thabah, and P. Saha, “Reducing Quantum Cost for the Reversible Realization of Densely-Packed-Decimal Converters” IJE TRANSACTIONS B: Applications vol. 34, no. 05, pp. 184-191, May 2021.
29. R. U. Ahmed, E.A. Vijaykumar, and P. Saha, “Sensitivity Analysis of the UTBSOI Transistor based Two-Stage Operational Transconductance Amplifier”, Electronics Journal, vol. 24, no. 2, pp. 75-80, Dec. 2020 .
28. S.D. Thabah, and P. Saha, “Improved
Signed Binary Multiplier Through New Partial Product Generation Scheme” Journal of Circuits, Systems and Computers,
vol. 29, no. 16, 2150162-1-21, 2021.
27.
S. K. Beura, A. A. Jawale, B. P.
Devi, and P. Saha, “On the Implementation of Multi-bit Inexact Adder
Cells and Application towards Image De-noising”, Electronics Journal, vol. 24, no. 1, pp. 35-44, 2020.
26.
S.D. Thabah, and P. Saha, “A
Low Quantum Cost Implementation of Reversible Binary-Coded-Decimal Adder”, Periodica
Polytechnica Electrical Engineering and Computer Science, vol. 64, no. 4, pp. 343-351, 2020.
25. R.U. Ahmed, E.A. Vijaykumar, H.S.
Ponakala, M. Y. V. Balaji, and P. Saha,
“Design of double-gate CMOS based two-stage operational transconductance
amplifier using the UTBSOI transistors” U.P.B. Sci. Bull., Series C, vol. 82,
no. 2, pp. 173-188, 2020.
24. R. U. Ahamed, and P. Saha, “Revisiting Analytical Models of N-Type Symmetric Double-Gate MOSFETs”, Electronics Journal, vol. 24, no. 1, pp. 17-34, 2020.
23. S. D. Thabah, M. Sonowal, R. U. Ahmed, and P. Saha, “Fast and Area Efficient Implementation of RSA Algorithm”, Procedia Computer Science, vol. 165, pp. 525-531, 2019.
22. R. U. Ahamed, S.D. Thabah, and P. Saha, “Design of New Multi-Column 5,5:4 Compressor Circuit Based on Double- Gate UTBSOI Transistors”, Procedia Computer Science, vol. 165, pp. 32-540, 2019.
21. R. U. Ahamed, and P. Saha, “Implementation Topology of Full Adder Cells”, Procedia Computer Science, vol. 165, pp.
676-683, 2019.
20. R. U. Ahamed, and P. Saha, “Modeling of Short P-Channel Symmetric Double-Gate MOSFET
for Low Power Circuit Simulation”, Periodica
Polytechnica Electrical Engineering and Computer Science, vol. 64, no. 1,
pp. 106-114, 2020.
19. S. D. Thabaha, and P. Saha, “Low Quantum Cost Realization of Reversible
Binary-Coded-Decimal Adder”, Procedia Computer Science, Accepted, 2019.
18. R. U. Ahamed, E. A.
Vijaykumar, and P. Saha,
“Single-Stage Operational Transconductance Amplifier Design based on gm/Id
Methodology” Electronics Journal,
vol. 23, no. 2, pp. 52-59, 2019.
17. S.D. Thabah, and P. Saha, “New Design Approaches of Reversible BCD Encoder using
Peres and Feynman Gates” ICT
Express, vol. 6, no. 1, pp. 38-42, 2020.
16. P. Saha, and P. Samanta, “Design and
Architecture of new 11:2 Decimal Compressors” Sadhana, vol. 44, no. 5, 125(1-12), 2019
15. S.D. Thabah, M.
Sonowal, and P. Saha, “On the Design
of Efficient Residue-to-Binary Converters” Procedia
Computer Science, vol. 132, pp. 816-823, 2018.
14. D. Kumar, P. Saha, and A. Dandapat,
“Vedic Algorithm for Cubic Computation and VLSI Implementation” Engineering
Science and Technology, an International Journal (Elsevier), Vol. 20, no. 5, pp. 1494-1499, Oct. 2017.
13. D. Kumar, P. Saha, and A. Dandapat,
“Hardware implementation methodologies of fixed point division algorithms” Int.
J. of Smart Sensing and Intelligent System, vol. 10, no. 3, pp. 630-645,
Sept. 2017.
12. S.D. Thabah, M. Sonowal, and P. Saha,
“Experimental Studies on Multi Operand Adders” Int. J. of Smart Sensing and
Intelligent System, vol. 10, no. 2, 2017,
pp. 327-340, June 2017.
11. A. Shadap, P. Saha, “Discrete Fourier
transformation processor based on complex radix (1 + j) number system”, Engineering
Science and Technology, an International Journal(Elsevier), Vol. 20, no. 1,
pp. 80-88, Feb. 2017.
10. P. Saha, D. Kumar “A new algorithm for the Computation of the Decimals of the
Inverse,” Computer Science & Engineering and Electrical Engineering,
Scientia Iranica, vol. 24, no. 3, 1363-1372, 2017.
9. P. Saha, D. Kumar, P. Bhattacharyya, and
A. Dandapat, “Design of 64-bit squarer based on Vedic mathematics,” Journal
circuit systems and computers, vol. 22, no. 7, 2014, pp. 1450092- 1-19.
8. P. Saha, P. Bhattacharyya, and A.
Dandapat, “Improved Floating Point Multiplier Design Based on Canonical Sign
Digit”, Int. J. of Technology, vol. 5, no. 1, 2014, pp. pp. 22-31.
7. P. Saha,
D. Kumar, P. Bhattacharyya, and A. Dandapat, “Vedic Division Methodology for
High Speed VLSI Applications”, Journal of
Engineering, IET, Vol. 2014, No. 2, 2014, pp. 51-59
6. P. Saha, A. Banerjee, A. Dandapat, and P. Bhattacharyya,
“A High Speed Multiplier using High Accuracy Floating Point Logarithmic Number
System”, Computer Science & Engineering and Electrical Engineering,
Scientia Iranica, vol. 21, no. 3, 2013, pp.
826-841.
5. P. Saha, A. Banerjee, P. Bhattacharyya,
and A. Dandapat, “Improved Matrix Multiplier Design for High Speed DSP
Applications”, IET Circuits Devices and Systems, vol. 8, no. 1, pp. 27-37, Jan 2014.
4. P. Saha, A. Banerjee, A. Dandapat, and P.
Bhattacharyya, “ASIC Design of a High Speed Low Power Circuit for Calculation
of Factorial of 4-Bit Numbers Based on Ancient Vedic Mathematics”, Microelectronics
Journal (Elsevier), vol. 42, no. 12, 2011, pp. 1343-1352, Dec. 2011.
3. P. Saha, A. Banerjee, A. Dandapat, and P.Bhattacharyya, “ASIC Implementation of High
Speed Processor for Calculating Discrete Fourier Transformation using Circular
Convolution Technique”, Int. J. of World Scientific and Engineering Academy
and Society (WSEAS), vol. 10, no. 8, pp. 278-288, Aug. 2011. (ISSN:
1109-2734).
2. P. Saha, A. Banerjee, A. Dandapat, and P.
Bhattacharyya, “Vedic Mathematics Based 32-Bit Multiplier Design for High Speed
Low Power Processor”, Int. J. of Smart Sensing and Intelligent System,
vol. 4, no. 2, 2011, pp. 268-284, June
2011. (ISSN: 1178-5608).
1. P. Saha, A. Banerjee, and A. Dandapat, “High Speed Low Power Complex Multiplier Design Using Parallel Adders and Subtractors”, Int. J. on Electronic and Electrical Engineering, (IJEEE),vol. 07, no. 11, 2009, pp. 38-46, Nov. 2009. (ISSN: 0974-2042).
Book Chapter:
5. P.
Saha, R.U. Ahmed, and S. D. Thabah, “Design and Implementation of Multi Operand
4. M.
Roy, A. Das, B. Neogi, and P. Saha, “Healthcare 4.0 in Prospective of
Respiratory support system and Artificial Lung”, Intelligent Interactive
Multimedia Systems for e-Healthcare Applications, Healthcare 4.0 in Prospective
of Respiratory support system and Artificial Lung, Accepted 2020.
3. R. Ahmed, and P. Saha, “Power and Delay Comparison of 7:3 Compressor Designs Based on Different Architectures of XOR Gate” G. Ranganathan et al. (eds.), Inventive Communication and Computational Technologies, vol. 89, pp. 461-469. https://doi.org/10.1007/978-981-15-0146-3_44
2. R. Ahmed and P. Saha, “Implementation Aspects of Multi-bit Adders using UTBSOI Transistors”, Yu-Dong Zhang et. al.(eds), Smart Trends in Computing and Communications, vol. 182, pp. 355-364.
1. D. Kumar and P. Saha, “Accelerating latency of binary division through Vedic methodology” Yu-Dong Zhang et. al. (eds), Smart Trends in Computing and Communications, vol. 182, pp. 365-378.
Conference proceedings:
17. S. K. Beura, J. Samanta, B.P. Devi, P.
Saha, Floating Point Adder using Inexact Mantissa Adder” IEEE Int. Conf. on
Computing and Communication Systems (I3CS), Shillong, India, 2023, pp. 1-5.
16. T. Maity, P. Giri, R. Sasmal, N. Biswas,
S. Das, P. K. Maity, P. Saha, J. Samanta,
Design of Smart IoT based Gas Leakage Detection and Prevention Device
for Hydrogen Station, Int. Conf. on Communication, Devices and Computing ,
Accepted 2023.
15.
M. Roy, A. Das, R. Biswas, B. Neogi, and P. Saha, “Mathematical Modeling
of Respiratory System Introducing Electrical Control Function Analogy”, Int.
Conf. on Communication, Devices and Computing, Aug. 16-18, 2021.
14.
S. K. Beura, G. A. Prabhakar, S. M. Mahanta, B. P. Devi and P. Saha, “Design and
Analysis of Inexact 3:2 Compressor based Radix-4 Multiplier towards Image
Multiplication” Int. Conf. on Computing Communication and Networking Technologies, 6th
-8th July, 2021, pp. 01-06.
13. S. Roy, D. Kumar, A. Dandapat, and P. Saha, “Discretized Sinusoidal
Waveform Generators for Signal Processing Applications”, IEEE
Int. Conf. on Trends in Electronics and Informatics, pp. 1350-1353,
2018.
12. D. Phiamphu, P. Saha, “Redesigned the
Architecture of Extended-Euclidean Algorithm for Modular Multiplicative Inverse
and Jacobi symbol, IEEE Int. Conf.
on Trends in Electronics and Informatics, pp. 1345-1349, 2018.
11. R.
Ahmed, P. Saha, “Modeling of
Threshold Voltage and Subthreshold Current for P-Channel Symmetric Double-Gate
MOSFET in Nanoscale Regime” IEEE Int.
Symp. on Nanoelectronic and Information Systems, pp. 179-183, 2017.
10. P.
Saha, P. Samanta, D. Kumar, “4:2 and 5:2 Decimal Compressors,” IEEE Int.
Conf. on Intelligent Systems, Modelling and Simulation, pp. 424-429,
Jan. 2016.
9. D. Kumar, A. Sharma, and P. Saha “Integer
Division Technique for Signal Processing Applications, Int. Conf. on Ubiquitous Information
Management and Communication (ACM), pp. 52 (1-4), 2015.
8. P. Saha, D. Kumar, and A. Sharma, “Implementation of High-Speed Processor for
Computing Convolution Sum for DSP Applications, Int. Conf. on Ubiquitous Information Management and Communication (ACM),
pp. 51(1-6), 2015.
7. P. Saha, D. Kumar, P.
Bhattacharyya, A. Dandapat, “Reciprocal unit based on Vedic mathematics for
signal processing applications” IEEE Symp. on Electronic System Design,
2013, pp. 41-45.
6. P. Saha, D. Kumar, P.
Bhattacharyya, A. Dandapat, “ASIC Implementation of High Speed Processor for
Computing Fast Hartley Transformation”, IEEE Conf. on Advanced Electronics
System, 2013, pp. 334-336.
5. P. Saha, A. Banerjee, A.
Dandapat, P. Bhattacharyya, “Design of High Speed Vedic Multiplier for Decimal
Number System”, IEEE Symp. on VLSI Design
and Testing, VDAT-12, 2012.
4. P. Saha, A. Banerjee, P.
Bhattacharyya, A. Dandapat, “Vedic Divider: Novel Architecture (ASIC) for High
Speed VLSI Applications”, IEEE, Int. Symp. on Electronic System Design,
pp. 67-71, 2011.
3. P. Saha, A. Banerjee, P.
Bhattacharyya, A. Dandapat, “High Speed ASIC Design of Complex Multiplier Using
Vedic Mathematics”, IEEE, Techsym,
pp. 237-241, 2011.
2. P. Saha, A. Banerjee, I.
Banerjee and A. Dandapat, “High Speed Low Power Floating Point Multiplier
Design Based on CSD (Canonical Sign Digit)”; IEEE Symp. on VLSI Design and
Testing, VDAT-10, 2010.
1. P.
Saha, A.Banerjee and A.Dandapat,“Low power and High Speed Factorial
Design in 22nm Technology” in Proc. of the AIP, Int. Conf. on Nanomaterials
and Nanotechnology, pp. 294-301, 2010.
Previous/Other Semester/Year
PhD
|
Sl. No. |
Name |
Roll No |
Thesis Title |
Competition Year |
Supervision |
Status |
|
1. |
Rekib Uddin Ahmed |
P16EC001 |
Design and Analysis of
Computational Circuits using Multi-Gate Nanoscale Device |
2021 |
Supervisor |
Completed |
|
2. |
Sheba Diamond Thabah |
P17EC004 |
Reduction Of Power Consumption Of Computational Arithmetic Circuits Using Reversible Logic Design |
2022 |
Supervisor |
Completed |
|
3. |
Srikant Kumar Beura |
P18EC001 |
Arithmetic Circuits for Error Tolerant
Applications: A Way Towards Implementation, Circuit Level Optimization And
Analysis |
2023 |
Co-Supervisor Supervisor- Dr. B. P. Devi |
Completed |
|
4. |
Moupali Roy |
P20EC002 |
Lung Circuit Analysis |
-- |
Co-Supervisor Br. B. Neogi |
Ongoing |
|
5. |
Seenivasan M A |
P21EC005 |
Neuromorphic Computing |
-- |
Supervisor |
Ongoing |
M.Tech
|
Sl. No. |
Name |
Roll No |
Thesis Title |
Competition Year |
Supervision |
|
1. |
Anidaphi Shadap |
T14EC001 |
Design of Arithmetic
Co-processor using complex base
(-1+j) |
2016 |
Supervisor |
|
2. |
Puja Samanta |
T14EC006 |
Arithmetic Circuits Implementation Based on Unconventional
Binary Coded Decimal Number System |
2016 |
Supervisor |
|
3, |
Vinita Kumari |
T15EC006 |
Adder And
Multiplier Using Residue Arithmetic |
2017 |
Supervisor |
|
4. |
Sheba Diamond Thabah |
T15EC010 |
Fast and Area Efficient Implementation of RSA Algorithm |
2017 |
Supervisor |
|
5. |
Dongmuanthang Phiamphu |
T16EC006
|
Hardware Implementation Of Modular Multiplicative Inverse And Jacobi Symbol |
2018 |
Supervisor |
|
6. |
Chisimey Bijimchi G Momin |
T16EC007
|
Field Adders and Multipliers for ECC |
2018 |
Supervisor |
|
7. |
Siddhartha Roy |
T16EC008 |
Discretized Sinusoidal Waveform Generators |
2018 |
Supervisor |
|
8. |
Eklare Akshay Vijaykumar |
T17EC001 |
Sizing of DG-CMOS for An Analog Circuit Application |
2019 |
Supervisor |
|
9. |
Sudesna Manjari Mahanto |
T19EC 009 |
Design and Implementation of Inexact 8×8 Radix-4 Booth Multipliers |
2021 |
Supervisor |
|
10. |
Adarsh V Parekkattil |
T21EC 003 |
A 65-nm Reliable 6T CMOS SRAM Cell with Minimum Size Transistors |
2023 |
Supervisor |
|
11. |
Harsh Raj Thakur |
T21EC 001 |
Spiral Neural Network (Digital Implementation) |
2024 |
Supervisor |
B. Tech
|
Sl. No. |
Name |
Roll No |
Thesis Title |
Competition Year |
Supervision |
|
1. |
P. Hemant Sai And Mangam Yogi |
B14EC 007 B14EC 028 |
Design of CMOS Opamp using Double Gate UTBSOI MOSFET |
2018 |
Supervisor |
|
2. |
Sanborlang I. Amdep and Arkyson Rani |
B17EC 004 B14EC 019 |
Compressor Design |
2018 |
Supervisor |
|
3. |
Rohit Kumar and Sonu Kumar |
B15EC 033 B15EC034 |
Design of an Amphibious Robot for
Surf zone Operation |
2019 |
Supervisor |
|
4. |
Sonalika Prasad And Rahul Kumar |
B15EC 003 B15EC 028 |
Smart Helmet |
2019 |
Supervisor |
|
5. |
BALAMHASHWA SYIEMLIEH, KETHIRI NARSIMHA REDDY, |
B16EC015 B16EC019 |
Design of Binary Multiplier using Approximate 4:2
Compressor |
2020 |
Supervisor |
|
6. |
WanchiDoraMSangma VikalpKaushik TapsriBMarak |
B17EC031 B17EC032 B17EC033 |
VLSI Implementation of Legendre Symbol |
2021 |
Supervisor |
|
7. |
Lamphrang Lanong and Teilang Lyngdoh |
B18EC 015 B18EC 016 |
Design and study types of adders and multipliers for designing
fractional multiplier |
2022 |
Supervisor |
|
8. |
Budi Manoj Kumar and and Nasaram Hemanth |
B19EC 019 B19EC 027 |
Design of Floating-Point Adders with Rounding |
2023 |
Supervisor |
|
9. |
M Sandeep Kumar Gupta and
Divya Rathore
|
B20EC032 B20EC017 |
Neuromorphic Computing |
2024 |
Supervisor |
|
10. |
Ankit Kumar and Pratibha Kumari |
B20EC028 B20EC016 |
Spiral Neural Networks |
2024 |
Supervisor |
