1.  Content addressable memory
2.  Low-power high-speed VLSI
3.  Low-power digital circuits

1.  Short Term Course on High Speed Communication Circuits under SMDP-C2SD Project, 25 – 30 June, 2018, IIT Guwahati, India.
2.  IEEE International Conference on Innovations in Electronics, Signal Processing & Communication (IESC 2017), April 6-7, 2017, NIT Meghalaya, India
3.  Instruction Enhancement Programme (IEP) on Cadence Tools under SMDP-C2SD Project, December 14-16, 2016, IIT Delhi, India
4.  DST Sponsored Workshop on Future Challenges in Wireless Communication and Signal Processing, August 7-8, 2015, NIT Meghalaya, India

Journal:

1. S. W. Hussain, T. V. Mahendra, S. Mishra and A. Dandapat, “Match-Lin Division and Control to Reduce Power Dissipation in Content Addressable Memory,” in IEEE Transactions on Consumer Electronics, vol. 64, no. 3, pp. 301-309, Aug. 2018. (DOI: 10.1109/TCE.2018.2859623)
2.  T. V. Mahendra, S. W. Hussain, S. Mishra and A. Dandapat, “Precharge free dynamic content addressable memory,” in Electronics Letters, vol. 54, no. 9, pp. 556-558, May 2018. (DOI: 10.1049/el.2018.0592)

Conference:

1. . K. B. Singh, S. W. Hussain, T. V. Mahendra, and C. V. R. Rao, “Implementation of OFDM and Pulsed-OFDM,” in IEEE 15th International Conference on Information Technology (ICIT), Bhubaneswar, 2016, pp. 110-113. (DOI: 10.1109/ICIT.2016.033 )