ELECTRONICS & COMMUNICATION ENGINEERING

Head of Department

Dr. Pradeep Kumar Rathore
Ph.D(IIT Delhi)

E-mail:
hod.ec@nitm.ac.in

Faculty

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Dr. Jagritee Talukdar Assistant Professor

Ph.D. in Microelectronics and VLSI, National Institute of Technology Silchar

jagritee.talukdar@nitm.ac.in

Research Interest

Conventional and non-conventional semiconductor devices and materials, Sensors, TMDC materials.

Education Qualification

Ph.D. in Microelectronics and VLSI, National Institute of Technology Silchar

International Jorunals

1.     J. Talukdar, Malvika, B. Das, G. Rawat and K. Mummaneni,” Source engineered TFET for digital inverters application” Physica Scripta, vol. 99, no.4, 2024, 10.1088/1402-4896/ad338b. (I.F. 2.6)

2.     J. Talukdar, G. Rawat, and K. Mummaneni, “Analytical Modeling and TCAD Simulation for Subthreshold Characteristics of Asymmetric Tunnel FET” Materials Science in Semiconductor Processing, vol: 142, pp: 106482, 2022. (I.F. 4.2)

3.     J. Talukdar, G. Rawat and K. Mummaneni, "Dielectrically Modulated Single and Double Gate Tunnel FET based Biosensors for Enhanced Sensitivity," IEEE Sensors Journal, vol. 21, no. 23, pp. 26566-26573, 1 Dec.1, 2021, doi: 10.1109/JSEN.2021.3122582. (I.F. 4.3).

4.     J. Talukdar, K. Mummaneni, A Reliability Study of Non-uniform Si TFET with Dual Material Source: Impact of Interface Trap Charges and Temperature. Silicon (2021). Vol: 14, pp: 4515–4521 https://doi.org/10.1007/s12633-021-01224-y. (I.F. 2.8).

5.     J. Talukdar, B. Choudhury, K. Mummaneni, Impact of temperature counting the effect of back gate bias on the performance of extended source tunnel FET (ESTFET) with ?p+ SiGe pocket layer, Applied Physics A, 127 (24), 2021. (I.F. 2.5).

6.     J. Talukdar, K. Mummaneni, A nonuniform silicon TFET design with dual material source and compressed drain, Applied Physics A, 126, (81) (2020) DOI: https://doi.org/10.1007/s00339-019-3266-5. (I.F. 2.5)

7.     J. Talukdar, G. Rawat, K. Singh, K. Mummaneni, Comparative Analysis of the Effects of Trap Charges on Single- and Double-Gate Extended-Source Tunnel FET with dp+ SiGe Pocket Layer, Journal of Electronic Materials, 49(7), (2020), 4333-4342.(I.F. 2.2)

8.     J. Talukdar, G. Rawat, K. Singh, K. Mummaneni, Low Frequency Noise Analysis of Single Gate Extended Source Tunnel FET, Silicon (2020), 13, pages3971–3980 (2021) https://doi.org/10.1007/s12633-020-00712-x.

9.     J. Talukdar, G. Rawat, K. Singh, B. Choudhury, K. Mummaneni, Device Physics Based Analytical Modeling for Electrical Characteristics of Single Gate Extended Source Tunnel FET(SG-ESTFET), Superlattices and Microstructures, 148, 106725, 2020.(I.F.3.1)

10.  J. Talukdar, G. Rawat K. Mummaneni, A Novel Extended Source TFET with ?p+- SiGe Layer, Silicon, 12:2273–2281, (2019) doi: 10.1007/s12633-019-00321-3.

11.  J. Talukdar, G. Rawat, K. Mummaneni, Noise behaviour and Reliability Analysis of Non-Uniform Body Tunnel FET with Dual Material Source, Microelectronics Reliability, vol. 131, April 2022, 114510 (I.F. 1.6).

12.  J. Talukdar, G. Rawat, K. Mummaneni, Highly Sensitivity Non-Uniform Tunnel FET based Biosensor using Source Engineering. Materials Science and Engineering B, Vol. 293, July 2023, 116455.(I.F.3.9)

13.  A. J. Mondal, J. Talukdar, B. K.Bhattacharyya, “Estimation of frequency and amplitude of ring oscillator built using current sources” Ain Shams Engineering Journal, vol. 11, no. 3, pp- 677-686, (I.F. 6).

14.  A. J. Mondal, J. Talukdar, B. K. Bhattacharyya, “Variation aware design of controlled voltage swing ring oscillator” International Journal of Electronics, https://doi.org/10.1080/00207217.2019.1636307,vol:107, pp-99-124.Dec 2018. (I.F.1.1).

15.  V. Sharma, S. Kumar, J. Talukdar, K. Mummaneni, G. Rawat, “Source pocket-engineered hetero-gate dielectric SOI Tunnel FET with improved performance”, Materials Science in Semiconductor Processing, 143:106541, 2022. (I.F. 4.2).

16.  Malvika, J. Talukdar, V. Kumar, B. Choudhuri, K. Mummaneni, Comparative Analysis of Noise behavior of Highly Doped Double Pocket Double?Gate and Single?Gate Negative Capacitance FET, Journal of Electronic Materials, vol:52, https://doi.org/10.1007/s11664-023-10558-9, 2023.

17.  K. Nikhil, K. M. C. Babu, J. Talukdar, E. Goel, A Simulation Study of the Effect of Trap Charges and Temperature on Performance of Dual Metal Strip Double Gate TFET, Silicon, 16, 525–534 (2024). https://doi.org/10.1007/s12633-023-02633-x.

18.  Malvika, J. Talukdar, B. Choudhuri, K. Mummaneni, Analysis of Noise Behavior and Reliability of Pocket Doped Negative Capacitance FET under the Impact of Trap Charges and Temperature, Microelectronics Reliability, vol: 152, January 2024, 115301, https://doi.org/10.1016/j.microrel.2023.115301.

19.  J. Talukdar and B. Muralidharan, "Performance analysis of optically gated MoS2 photosensor for visible light detection," in IEEE Sensors Journal, vol. 24, no. 15, pp. 23810-23817, 1 Aug.1, 2024, doi: 10.1109/JSEN.2024.3416374.

International Conferences

1.    J. Talukdar and K. Mummaneni, "Impact of temperature and different types of trap charges on noise behavior of Non-uniform Body with Dual Material Source TFET (NUTFET-DMS)," 2021 Devices for Integrated Circuit (DevIC), 2021, pp. 541-544, doi: 10.1109/DevIC50843.2021.9455914.

2.    J. Talukdar and K. Mummaneni, "Noise Behavior of SG-ESTFET with Various Interface Trap Charges," 2020 International Conference on Computational Performance Evaluation (ComPE), 2020, pp. 222-225, doi: 10.1109/ComPE49325.2020.9200121.

3.    J. Talukdar and B. Das, "An improved TIQ comparator based 3-bit flash ADC," 2017 1st International Conference on Electronics, Materials Engineering and Nano-Technology (IEMENTech), 2017, pp. 1-4, doi: 10.1109/IEMENTECH.2017.8076965.

4.    J. Talukdar, G. Amarnath, K. Mummaneni (2022) Flicker Noise Analysis of Non-uniform Body TFET with Dual Material Source (NUTFET-DMS), “Micro and Nanoelectronics Devices, Circuits and Systems”, vol 781. Springer, Singapore. https://doi.org/10.1007/978-981-16-3767-4_23.

5.    J. Talukdar, Malvika, Basab Das, Kavicharan Mummaneni, Sensitivity analysis of Non-uniform TFET with dual material source-based biosensor, IEEE International Symposium on Smart Electronic Systems, 2023, DOI: 10.1109/iSES54909.2022.00131.

6.    J. Talukdar, P. Saksena, K. Mummaneni (2022) Design and analysis of Non-Uniform body with dual material source FET based digital Inverter, Micro and Nanoelectronics Devices, Circuits and Systems, DOI: 10.1007/978-981-19-2308-1_17.

7.    M. Shashikumar, B.J. Das, J. Talukdar, K. Mummaneni (2022) Radix-10 Multiplier Implementation with Carry Skip Adder Using Verilog. In: Lenka T.R., Misra D., Biswas A. (eds) Micro and Nanoelectronics Devices, Circuits and Systems. Lecture Notes in Electrical Engineering, vol 781. Springer, Singapore. https://doi.org/10.1007/978-981-16-3767-4_38

8.    A. Zade, S. K. Singha, J. Talukdar, A. Prathima, and K. Mummaneni, (2022) “Implementation of Arithmetic Logic Unit Using Area-Efficient Adder”, Proceedings of the International Conference on Computational Intelligence and Sustainable Technologies, Algorithms for Intelligent Systems, https://doi.org/10.1007/978-981-16-6893-7_5.

9.    Malvika, J. Talukdar, B. Choudhuri, K. Mummaneni, A simulation study of the effect of ferroelectric thickness and oxide variation on the performance of Highly Doped Double Pocket Double Gate NCFET based inverter, IEEE International Symposium on Smart Electronic Systems, 2023, DOI: 10.1109/iSES54909.2022.00132.

10. S. Halder, M. L. Saha, Malvika, J. Talukdar, K. Mummaneni, Design and Implementation of an Optimized High-Speed Vedic-Based Squarer Circuit Using Reversible Logic Gates, Micro and Nanoelectronics Devices, Circuits and Systems, 2023. Lecture Notes in Electrical Engineering, vol 1067. Springer, Singapore. https://doi.org/10.1007/978-981-99-4495-8_24.

11. Malvika, J. Talukdar, G. Rawat, B. Choudhuri, K. Mummaneni, Exploration of Graphene as Emerging 2D Material and its Applications: A Review, 4th International Conference on Frontiers in Computing and Systems (COMSYS-2023). (Presented).

12. J. Talukdar, B. Muralidharan, “Performance enhancement of donor impurity integrated MoS2 based TFET photosensor through dielectric alteration” International Conference on functional materials, 2024, Indian Institute of Technology Kharagpur.

13. J. Talukdar, B. Muralidharan “Performance improvement of trap charge infused MoS2 based TFET photosensor by dielectric engineering” 2024 8th IEEE Electron Devices Technology & Manufacturing Conference (EDTM), Bangalore, India, 2024, pp. 1-3, doi: 10.1109/EDTM58488.2024.10512324.

14. J. Talukdar, B. Muralidharan, Performance analysis of MoS2 based Ferroelectric Tunnel FET,  Graphene 2024, Madrid, Spain.

Work experience

Post doctoral fellow, IIT Bombay

Assistant Professor (Ad-hoc), Department of Electronics and Communication Engineering, Indian Institute of Information Technology Design and Manufacture Kurnool Andhra Pradesh